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These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMICA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package
SI3442DV Maximum Ratings
Symbol
Parameter
Ratings
Units
VDSS
Drain-Source Voltage
20
V
VGSS
Gate-Source Voltage
8
V
ID
Drain Current Continuous (Note 1a) Pulsed
4.1
A
15
PD
Maximum Power Dissipation (Note 1a) (Note 1b) (Note 1c)
1.6
W
1
0.8
TJ, TSTG
Operating and Storage Junction Temperature Range
55 to +150
°C
SI3442DV Features
·4.1 A, 20 V. RDS(ON) = 0.06 W @ VGS = 4.5 V RDS(ON) = 0.075 W @ VGS =2.7 V. ·Proprietary SuperSOTTM-6 package design using copper ·ead frame for superior thermal and electrical capabilities. ·High density cell design for extremely low RDS(ON). ·Exceptional on-resistance and maximum DC current capability.