SLA7051MLF871, SLA7051MLF872, SLA7052MLF871 Selling Leads, Datasheet
MFG:allegro Package Cooled:N/A D/C:09+
SLA7051MLF871, SLA7051MLF872, SLA7052MLF871 Datasheet download

Part Number: SLA7051MLF871
MFG: allegro
Package Cooled: N/A
D/C: 09+
MFG:allegro Package Cooled:N/A D/C:09+
SLA7051MLF871, SLA7051MLF872, SLA7052MLF871 Datasheet download

MFG: allegro
Package Cooled: N/A
D/C: 09+
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Datasheet: SLA7051MLF871
File Size: 360201 KB
Manufacturer: ALLEGRO [Allegro MicroSystems]
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PDF/DataSheet Download
Datasheet: SLA0201
File Size: 33205 KB
Manufacturer: SANKEN [Sanken electric]
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PDF/DataSheet Download
Datasheet: SLA7052MLF871
File Size: 673085 KB
Manufacturer: allegromicro
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Combining low-power CMOS logic with high-current, high-voltage power FET outputs, the SLA7051M translator/driver provides complete control and drive for a two-phase unipolar stepper motor with internal fixed off time, pulse-width modulation (PWM) control of the output current in a power multi-chip module (PMCMT).
The CMOS logic section provides the sequencing logic, direction, full/half-step control, synchronous/asynchronous PWM operation, and a "sleep" function. The minimum CLOCK input is an ideal fit for applications where a complex µP is unavailable or overburdened. TTL or LSTTL may require the use of appropriate pull-up resistors to ensure a proper input-logic high. For PWM current control, the maximum output current is determined by the user&primes selection of a reference voltage and sensing resistor. The NMOS outputs are capable of sinking up to 2 A and withstanding 46 V in the off state. Ground-clamp and flyback diodes provide protection against inductive transients. Special power-up sequencing is not required.
Full-step (2 phase) and half-step operation are externally selectable. Two-phase drive energizes two adjacent phases in each detent position (AB-BC-CD-DA). This sequence mode offers an improved torquespeed product, greater detent torque, and is less susceptable to motor resonance. Half-step excitation alternates between the one-phase and two-phase modes (A-AB-B-BC-C-CD D-DA), providing an eight-step sequence.
Combining low-power CMOS logic with high-current, high-voltage power FET outputs, the SLA7051M translator/driver provides complete control and drive for a two-phase unipolar stepper motor with internal fixed off time, pulse-width modulation (PWM) control of the output current in a power multi-chip module (PMCMT).
The CMOS logic section provides the sequencing logic, direction, full/half-step control, synchronous/asynchronous PWM operation, and a "sleep" function. The minimum CLOCK input is an ideal fit for applications where a complex µP is unavailable or overburdened. TTL or LSTTL may require the use of appropriate pull-up resistors to ensure a proper input-logic high. For PWM current control, the maximum output current is determined by the user&primes selection of a reference voltage and sensing resistor. The NMOS outputs are capable of sinking up to 2 A and withstanding 46 V in the off state. Ground-clamp and flyback diodes provide protection against inductive transients. Special power-up sequencing is not required.
Full-step (2 phase) and half-step operation are externally selectable. Two-phase drive energizes two adjacent phases in each detent position (AB-BC-CD-DA). This sequence mode offers an improved torquespeed product, greater detent torque, and is less susceptable to motor resonance. Half-step excitation alternates between the one-phase and two-phase modes (A-AB-B-BC-C-CD D-DA), providing an eight-step sequence.
Combining low-power CMOS logic with high-current, high-voltage power FET outputs, the SLA7051M translator/driver provides complete control and drive for a two-phase unipolar stepper motor with internal fixed off time, pulse-width modulation (PWM) control of the output current in a power multi-chip module (PMCMT).
The CMOS logic section provides the sequencing logic, direction, full/half-step control, synchronous/asynchronous PWM operation, and a "sleep" function. The minimum CLOCK input is an ideal fit for applications where a complex µP is unavailable or overburdened. TTL or LSTTL may require the use of appropriate pull-up resistors to ensure a proper input-logic high. For PWM current control, the maximum output current is determined by the user&primes selection of a reference voltage and sensing resistor. The NMOS outputs are capable of sinking up to 2 A and withstanding 46 V in the off state. Ground-clamp and flyback diodes provide protection against inductive transients. Special power-up sequencing is not required.
Full-step (2 phase) and half-step operation are externally selectable. Two-phase drive energizes two adjacent phases in each detent position (AB-BC-CD-DA). This sequence mode offers an improved torquespeed product, greater detent torque, and is less susceptable to motor resonance. Half-step excitation alternates between the one-phase and two-phase modes (A-AB-B-BC-C-CD D-DA), providing an eight-step sequence.
Combining low-power CMOS logic with high-current, high-voltage power FET outputs, the SLA7051M translator/driver provides complete control and drive for a two-phase unipolar stepper motor with internal fixed off time, pulse-width modulation (PWM) control of the output current in a power multi-chip module (PMCMT).
The CMOS logic section provides the sequencing logic, direction, full/half-step control, synchronous/asynchronous PWM operation, and a "sleep" function. The minimum CLOCK input is an ideal fit for applications where a complex µP is unavailable or overburdened. TTL or LSTTL may require the use of appropriate pull-up resistors to ensure a proper input-logic high. For PWM current control, the maximum output current is determined by the user&primes selection of a reference voltage and sensing resistor. The NMOS outputs are capable of sinking up to 2 A and withstanding 46 V in the off state. Ground-clamp and flyback diodes provide protection against inductive transients. Special power-up sequencing is not required.
Full-step (2 phase) and half-step operation are externally selectable. Two-phase drive energizes two adjacent phases in each detent position (AB-BC-CD-DA). This sequence mode offers an improved torquespeed product, greater detent torque, and is less susceptable to motor resonance. Half-step excitation alternates between the one-phase and two-phase modes (A-AB-B-BC-C-CD D-DA), providing an eight-step sequence.
Combining low-power CMOS logic with high-current, high-voltage power FET outputs, the SLA7052M translator/driver provides complete control and drive for a two-phase unipolar stepper motor with internal fixed off time, pulse-width modulation (PWM) control of the output current in a power multi-chip module (PMCMT).
The CMOS logic section provides the sequencing logic, direction, full/half-step control, synchronous/asynchronous PWM operation, and a "sleep" function. The minimum CLOCK input is an ideal fit for applications where a complex µP is unavailable or overburdened. TTL or LSTTL may require the use of appropriate pull-up resistors to ensure a proper input-logic high. For PWM current control, the maximum output current is determined by the user&primes selection of a reference voltage and sensing resistor. The NMOS outputs are capable of sinking up to 3 A and withstanding 46 V in the off state. Ground-clamp and flyback diodes provide protection against inductive transients. Special power-up sequencing is not required.
Full-step (2 phase) and half-step operation are externally selectable. Two-phase drive energizes two adjacent phases in each detent position (AB-BC-CD-DA). This sequence mode offers an improved torquespeed product, greater detent torque, and is less susceptable to motor resonance. Half-step excitation alternates between the one-phase and two-phase modes (A-AB-B-BC-C-CD D-DA), providing an eight-step sequence.
Combining low-power CMOS logic with high-current, high-voltage power FET outputs, the SLA7052M translator/driver provides complete control and drive for a two-phase unipolar stepper motor with internal fixed off time, pulse-width modulation (PWM) control of the output current in a power multi-chip module (PMCMT).
The CMOS logic section provides the sequencing logic, direction, full/half-step control, synchronous/asynchronous PWM operation, and a "sleep" function. The minimum CLOCK input is an ideal fit for applications where a complex µP is unavailable or overburdened. TTL or LSTTL may require the use of appropriate pull-up resistors to ensure a proper input-logic high. For PWM current control, the maximum output current is determined by the user&primes selection of a reference voltage and sensing resistor. The NMOS outputs are capable of sinking up to 3 A and withstanding 46 V in the off state. Ground-clamp and flyback diodes provide protection against inductive transients. Special power-up sequencing is not required.
Full-step (2 phase) and half-step operation are externally selectable. Two-phase drive energizes two adjacent phases in each detent position (AB-BC-CD-DA). This sequence mode offers an improved torquespeed product, greater detent torque, and is less susceptable to motor resonance. Half-step excitation alternates between the one-phase and two-phase modes (A-AB-B-BC-C-CD D-DA), providing an eight-step sequence.
