T712., T7121, T71215K Selling Leads, Datasheet
MFG:5600 Package Cooled:TI D/C:03+
T712., T7121, T71215K
- Table of contents:
Info of T712.
Info of T7121
Info of T71215K
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About T7114
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Datasheet: T7114
File Size: 443387 KB
Manufacturer: ETC
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About T7121
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Datasheet: T7121
File Size: 701831 KB
Manufacturer: AGERE [Agere Systems]
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About T7114
PDF/DataSheet Download
Datasheet: T7114
File Size: 443387 KB
Manufacturer: ETC
Download : Click here to Download
T7121 General Description
The T7121 HDLC Interface for ISDN (HIFI-64) connects serial communications links carrying HDLC bitsynchronous data frames to 8-bit microcomputer systems.
There is an optional transparent mode of operation in which no HDLC processing is performed on user data. The device communicates with the system microprocessor as a memory-mapped peripheral and is controlled by reading and writing 19 internal registers.
The chip can be instructed to interrupt the microprocessor when it detects certain events requiring microprocessor attention. The HDLC transmitter and receiver are each buffered with 64-byte, first-infirst- out (FIFO) memory storage. The 64-byte buffer depth reduces the number of status polls or interrupts to be processed by the microprocessor, improving overall system efficiency. The major blocks are the microprocessor interface, transmit and receive FIFO memory buffers, HDLC processor, and a concentration highway interface (see Figure 1). The T7121 device is available in a 28-pin, plastic DIP or a 28-pin, plastic, small-outline, J-lead (SOJ) package for surface mounting.
T7121 Maximum Ratings
| Parameter |
Symbol |
Min |
Max |
Unit |
| dc Supply Voltage Relative to VSS |
VDD |
7 |
V | |
| Input Voltage Range |
VI |
VSS 0.5 |
VDD + 0.5 |
V |
| Storage Temperature Range |
Tstg |
40 |
125 |
°C |
T7121 Features
` Low-cost device for B-channel (64 kbits/s) or D-channel (16 kbits/s) data transport.
` Optional transparent mode-no HDLC framing is performed.
` Frame sync (FS) allows a slot-select feature to access an individual time slot in any TDM data stream (e.g., Lucent Technologies Microelectronics Group Concentration Highway Interface [CHI] or subset).
` Bit-masking option allows effective data rates of 8, 16, 24, 32, 40, 48, and 56 kbits/s.
` Maximum data rate up to 4.096 MHz.
` Serial data-transfer pins for direct connection to the Lucent ISDN line transceiver T7250C.
` Supports IOM2, K2, GCI, and SLD interface.
` Parallel microprocessor interface with either multiplexed or demultiplexed address and data lines for easy interface with any microprocessor.
` Single interrupt output signal with seven maskable interrupt conditions.
` Programmable interrupt modes.
` Memory-mapped read and write registers.
` TTL/CMOS compatible input/output.
` 3-state output pins to assist system diagnostics.
` Low-power 1.25 mm CMOS:
- 30 mW typical operation at 12 MHz.
- 5 mW standby mode (typical).
` HDLC transceiver:
- Stand-alone HDLC framing operation.
- 64-byte FIFO in both transmit and receive directions.
- Supports block-move instruction.
- Multiple frames allowed in FIFO.
- Programmable FIFO full- and empty-level interrupt.
` Optional transparent mode-no HDLC framing is performed.
` Frame sync (FS) allows a slot-select feature to access an individual time slot in any TDM data stream (e.g., Lucent Technologies Microelectronics Group Concentration Highway Interface [CHI] or subset).
` Bit-masking option allows effective data rates of 8, 16, 24, 32, 40, 48, and 56 kbits/s.
` Maximum data rate up to 4.096 MHz.
` Serial data-transfer pins for direct connection to the Lucent ISDN line transceiver T7250C.
` Supports IOM2, K2, GCI, and SLD interface.
` Parallel microprocessor interface with either multiplexed or demultiplexed address and data lines for easy interface with any microprocessor.
` Single interrupt output signal with seven maskable interrupt conditions.
` Programmable interrupt modes.
` Memory-mapped read and write registers.
` TTL/CMOS compatible input/output.
` 3-state output pins to assist system diagnostics.
` Low-power 1.25 mm CMOS:
- 30 mW typical operation at 12 MHz.
- 5 mW standby mode (typical).
` HDLC transceiver:
- Stand-alone HDLC framing operation.
- 64-byte FIFO in both transmit and receive directions.
- Supports block-move instruction.
- Multiple frames allowed in FIFO.
- Programmable FIFO full- and empty-level interrupt.
T7121 Connection Diagram
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