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T84S17D414-48, T85009W01, T8502

T84S17D414-48, T85009W01, T8502 Selling Leads, Datasheet

MFG:P&B  Package Cooled:Relay(DZ)  D/C:0103A+ 0108A+ 0044A+

T84S17D414-48, T85009W01, T8502 Picture

T84S17D414-48, T85009W01, T8502 Datasheet download

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Part Number: T84S17D414-48

 

MFG: P&B

Package Cooled: Relay(DZ)

D/C: 0103A+ 0108A+ 0044A+

 

 

 
 
 
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About T840-600B

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Datasheet: T840-600B

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Manufacturer: STMICROELECTRONICS [STMicroelectronics]

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About T8502

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Datasheet: T8502

File Size: 451352 KB

Manufacturer: AGERE [Agere Systems]

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  • T8502 EL

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  • T8502EL

  • Vendor: lucent Pack: SOP D/C: 98+& Qty: 4 Note: stock,TEL:86-0755-61329226,MSN:havinzhou@hotmail.com  Adddate: 2024-04-16
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  • Enoki Electronics Technology   China
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  • T8502 EL

  • Vendor: lucent Pack: SOP D/C: 98+& Qty: 4 Note: stock,TEL:86-0755-61329226,MSN:havinzhou@hotmail.com  Adddate: 2024-04-16
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  • T8502EL

  • Vendor: lucent Pack: SOP D/C: 98+& Qty: 4 Note: stock,TEL:86-0755-61329226,MSN:havinzhou@hotmail.com  Adddate: 2024-04-16
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  • Enoki Electronics Technology   China
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    Fax: 86-0755-82529412
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  • T8521AM

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  • T8533ML

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About T8502

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Datasheet: T8502

File Size: 451352 KB

Manufacturer: AGERE [Agere Systems]

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T8502 General Description

The T8502 and T8503 devices are single-chip, twochannel, m-law/A-law PCM codecs with filters. These integrated circuits provide analog-to-digital and digital-to-analog conversion. They provide the transmit and receive filtering necessary to interface a voice telephone circuit to a time-division multiplexed system. These devices are packaged in both 20-pin SOJs and 20-pin SOGs.

The T8502 differs from the T8503 in its timing mode. The T8502 operates in the delayed timing mode (digital data is valid one clock cycle after frame sync goes high), and the T8503 operates in the nondelayed timing mode (digital data valid when frame sync goes high) (see Figures 5 and 6).

T8502 Maximum Ratings

Parameter
Symbol
Min
Max
Unit
Storage Temperature Range
Tstg
55
150
°C
Power Supply Voltage
VDD
-
6.5
V
Voltage on Any Pin with Respect to Ground
-
-0.5
0.5 + VDD
V
Maximum Power Dissipation (package limit)
PD
-
600
mW

T8502 Features

` +5 V only
` Two independent channels
` Pin-selectable receive gain control
` Pin-selectable -law or A-law companding
` Automatic powerdown mode
` Low-power, latch-up-free CMOS technology
   - 40 mW/channel typical operating power dissipation
   - 12.5 mW/channel typical standby power dissipation
` Automatic master clock frequency selection
   - 2.048 MHz or 4.096 MHz
` Independent transmit and receive frame strobes
` 2.048 MHz or 4.096 MHz data rate
` On-chip sample and hold, autozero, and precision voltage reference
` Differential architecture for high noise immunity and power supply rejection
` Meets or exceeds ITU-T G.711-G.714 requirements and VF characteristics of D3/D4 (as per Bellcore PUB43801)
` Operating temperature range: 40°C to +85°C

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