TISP61511, TISP61511DR, TISP61512P Selling Leads, Datasheet
MFG:B(BOURNS) Package Cooled:SOP8 D/C:06+
TISP61511, TISP61511DR, TISP61512P Datasheet download
Part Number: TISP61511
MFG: B(BOURNS)
Package Cooled: SOP8
D/C: 06+
MFG:B(BOURNS) Package Cooled:SOP8 D/C:06+
TISP61511, TISP61511DR, TISP61512P Datasheet download
MFG: B(BOURNS)
Package Cooled: SOP8
D/C: 06+
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PDF/DataSheet Download
Datasheet: TISP61511D
File Size: 215060 KB
Manufacturer: POINN [Power Innovations Limited]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: TIS150-124
File Size: 302333 KB
Manufacturer: TRACOPOWER [TRACO Electronic AG]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: TISP61512P
File Size: 215060 KB
Manufacturer: POINN [Power Innovations Limited]
Download : Click here to Download
The TISP61511D and TISP61512P are dual forward-conducting buffered p-gate overvoltage protectors. They are designed to protect monolithic Subscriber Line Interface Circuits,SLICs, against overvoltages on the telephone line caused by lightning, ac power contact and induction. The TISP61511D and TISP61512P limit voltages that exceed the SLIC supply rail voltage.
The SLIC line driver section is typically poweredfrom 0 V (ground) and a negative voltage in the region of -10 V to -70 V. The protector gate is connected tothis negative supply. This references the protection (clipping) voltage to the negative supply voltage. As theprotection voltage will track the negative supply voltage the overvoltage stress on the SLIC is minimised.
Positive overvoltages are clipped to ground by diode forward conduction. Negative overvoltages are initially clipped close to the SLIC negative supply rail value. If sufficient current is available from the overvoltage, then the protector will crowbar into a low voltage on-state condition. As the current subsides the high holdingcurrent of the crowbar prevents d.c.latchup.
These monolithic protection devices are fabricated in ion-implanted planar vertical power structures for high reliability and in normal system operation they are virtually transparent. The buffered gate design reduces the loading on the SLIC supply during overvoltages caused by power cross and induction.
RATING | SYMBOL | VALUE | UNIT |
Repetitive peak off-state voltage, IG = 0, -40°C TJ85°C | VDRM | -100 | V |
Repetitive peak gate-cathode voltage, VKA = 0, -40°C TJ 85°C | VGKRM | -85 | V |
Non-repetitive peak on-state pulse current (see Notes 1 and 2) 10/1000 µs 5/310 µs 0.2/310 µs 1/20 µs 2/10 µs TJ = -40°C TJ = 25, 85°C |
ITSP | 30 40 40 90 120 170 |
A |
Non-repetitive peak on-state current, 50 Hz (see Notes 1 and 2) full-sine-wave, 20 ms 1 s |
ITSM | 5 3.5 |
A |
Non-repetitive peak gate current, half-sine-wave, 10 ms (see Notes 1and 2) | IGSM | 2 | A |
Junction temperature | TJ | -55 to +150 | °C |
Storage temperature range | Tstg | -55 to +150 | °C |