TMS320C31PQLA60, TMS320C31PQLEE, TMS320C32 Selling Leads, Datasheet
MFG:TI Package Cooled:QFP D/C:08+
TMS320C31PQLA60, TMS320C31PQLEE, TMS320C32 Datasheet download
Part Number: TMS320C31PQLA60
MFG: TI
Package Cooled: QFP
D/C: 08+
TMS320C31PQLA60, TMS320C31PQLEE, TMS320C32
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Info of TMS320C31PQLA60
Info of TMS320C31PQLEE
Info of TMS320C32
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About TMS0320F2810PBKAEP
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Datasheet: TMS0320F2810PBKAEP
File Size: 2134946 KB
Manufacturer: TI [Texas Instruments]
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About TMS0320F2810PBKAEP
PDF/DataSheet Download
Datasheet: TMS0320F2810PBKAEP
File Size: 2134946 KB
Manufacturer: TI [Texas Instruments]
Download : Click here to Download
About TMS320C32PCM40
PDF/DataSheet Download
Datasheet: TMS320C32PCM40
File Size: 1441290 KB
Manufacturer:
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TMS320C32 General Description
The TMS320C32 is the newest member of the TMS320C3x generation of digital signal processors (DSPs) from Texas Instruments. The TMS320C32 is an enhanced 32-bit floating-point processor manufactured in 0.7-mm triple-level-metal CMOS technology. The enhancements to the TMS320C3x architecture include a variable-width external-memory interface, faster instruction cycle time, power-down modes, two-channel DMA coprocessor with configurable priorities, flexible boot loader, relocatable interrupt-vector table, and edge- or level-triggered interrupts.
TMS320C32 Maximum Ratings
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V
Continuous power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . 1.95 W
Operating case temperature, TC (PCM (commercial) . . . . . . . . . . . . ... . . 0 to 85
(PCMA (extended) . . . . . . . . . . . . . 40 to 125
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . 55 to 150
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to VSS.
2. This value calculated for the 'C32-40. Actual operating power is less. This value was obtained under specially produced worst-case test conditions which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to the external bus at the maximum rate possible. See normal (IDD) current specification in the electrical characteristics table and refer the Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRU031).
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V
Continuous power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . 1.95 W
Operating case temperature, TC (PCM (commercial) . . . . . . . . . . . . ... . . 0 to 85
(PCMA (extended) . . . . . . . . . . . . . 40 to 125
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . 55 to 150
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to VSS.
2. This value calculated for the 'C32-40. Actual operating power is less. This value was obtained under specially produced worst-case test conditions which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to the external bus at the maximum rate possible. See normal (IDD) current specification in the electrical characteristics table and refer the Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRU031).
TMS320C32 Features
` High-Performance Floating-Point DSP
TMS320C32-60 (5 V) 33-ns Instruction Cycle Time 330 Million Operations Per Second (MOPS), 60 Million Floating-Point Operations Per Second (MFLOPS), 30 Million Instructions Per Second (MIPS)
TMS320C32-50 (5 V) 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS
TMS320C32-40 (5 V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS
` 32-Bit High-Performance CPU
` 16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations
` 32-Bit Instruction Word, 24-Bit Addresses
` Two 256 * 32-Bit Single-Cycle, Dual-Access On-Chip RAM Blocks
` Flexible Boot-Program Loader
` On-Chip Memory-Mapped Peripherals:
One Serial Port
Two 32-Bit Timers
Two-Channel Direct Memory Access (DMA) Coprocessor With Configurable Priorities
` Enhanced External Memory Interface That Supports 8-/16-/32-Bit-Wide External RAM for Data Access and Program Execution From 16-/32-Bit-Wide External RAM
` TMS320C30 and TMS320C31 Object Code Compatible
` Fabricated using 0.7 mm Enhanced Performance Implanted CMOS (EPICE) Technology by Texas Instruments (TIE)
` 144-Pin Plastic Quad Flat Package (PCM Suffix) 5 V
` Eight Extended-Precision Registers
` Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
` Two Low-Power Modes
` Two- and Three-Operand Instructions
` Parallel Arithmetic Logic Unit (ALU) and Multiplier Execution in a Single Cycle
` Block-Repeat Capability
` Zero-Overhead Loops With Single-Cycle Branches
` Conditional Calls and Returns
` Interlocked Instructions for Multiprocessing Support
` One External Pin, PRGW, That Configures the External-Program-Memory Width to 16 or 32 Bits
` Two Sets of Memory Strobes (STRB0 and STRB1) and One I/O Strobe (IOSTRB) Allow Zero-Glue Logic Interface to Two Banks of Memory and One Bank of External Peripherals
` Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation, External Memory Width, and Data Type Size
` STRB0 and STRB1 Memory Strobes Handle 8-, 16-, or 32-Bit External Data Accesses (Reads and Writes)
` Multiprocessor Support Through the HOLD and HOLDA Signals Is Valid for All Strobes
TMS320C32-60 (5 V) 33-ns Instruction Cycle Time 330 Million Operations Per Second (MOPS), 60 Million Floating-Point Operations Per Second (MFLOPS), 30 Million Instructions Per Second (MIPS)
TMS320C32-50 (5 V) 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS
TMS320C32-40 (5 V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS
` 32-Bit High-Performance CPU
` 16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations
` 32-Bit Instruction Word, 24-Bit Addresses
` Two 256 * 32-Bit Single-Cycle, Dual-Access On-Chip RAM Blocks
` Flexible Boot-Program Loader
` On-Chip Memory-Mapped Peripherals:
One Serial Port
Two 32-Bit Timers
Two-Channel Direct Memory Access (DMA) Coprocessor With Configurable Priorities
` Enhanced External Memory Interface That Supports 8-/16-/32-Bit-Wide External RAM for Data Access and Program Execution From 16-/32-Bit-Wide External RAM
` TMS320C30 and TMS320C31 Object Code Compatible
` Fabricated using 0.7 mm Enhanced Performance Implanted CMOS (EPICE) Technology by Texas Instruments (TIE)
` 144-Pin Plastic Quad Flat Package (PCM Suffix) 5 V
` Eight Extended-Precision Registers
` Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
` Two Low-Power Modes
` Two- and Three-Operand Instructions
` Parallel Arithmetic Logic Unit (ALU) and Multiplier Execution in a Single Cycle
` Block-Repeat Capability
` Zero-Overhead Loops With Single-Cycle Branches
` Conditional Calls and Returns
` Interlocked Instructions for Multiprocessing Support
` One External Pin, PRGW, That Configures the External-Program-Memory Width to 16 or 32 Bits
` Two Sets of Memory Strobes (STRB0 and STRB1) and One I/O Strobe (IOSTRB) Allow Zero-Glue Logic Interface to Two Banks of Memory and One Bank of External Peripherals
` Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation, External Memory Width, and Data Type Size
` STRB0 and STRB1 Memory Strobes Handle 8-, 16-, or 32-Bit External Data Accesses (Reads and Writes)
` Multiprocessor Support Through the HOLD and HOLDA Signals Is Valid for All Strobes
TMS320C32 Connection Diagram
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