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TS68230P10, TS683, TS68302

Table of contents:
Info of TS68230P10
Info of TS683
Info of TS68302

TS68230P10, TS683, TS68302 Selling Leads, Datasheet

MFG:MOT Package Cooled:DIP D/C:09+

TS68230P10, TS683, TS68302 Datasheet download

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Part Number: TS68230P10

MFG: MOT

Package Cooled: DIP

D/C: 09+

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TS68302 General Description

The IMP is a very large-scale integration (VLSI) device incorporating the main building blocks needed for the design of a wide variety of controllers. The device is especially suitable to applications in the communications industry. The IMP is the first device to offer the benefits of a closely coupled, industry-standard, TS68000/TS68008 microprocessor core and a flexible communications architecture. This multichannel communications device may be configured to support a number of popular industry interfaces, including those for the integrated services digital network (ISDN) basic rate and terminal adapter applications. Through a combination of architectural and programmable features, concurrent operation of different protocols is easily achieved using the IMP. Data concentrators, line cards, bridges, and gateways are examples of suitable applications for this versatile device.

The IMP is a high-density complementary metal-oxide semiconductor (HCMOS) device consisting of a S68000/TS68008 microprocessor core, a system integration block (SIB), and a communications processor (CP). The TS68302 block diagram is shown in Figure 1.

Note: GCI is sometimes referred to as IOM2.

TS68302 Maximum Ratings

Symbol	Parameter	Min	Max	Unit
P_D	Power Dissipation (typical at 16.67 MHz)⁽¹⁾	53	64	mA
P_D	Power Dissipation (typical at 8 MHz)⁽¹⁾	26	31	mA
LP_D	Low Power Mode Dissipation (typical at 16.67 MHz)⁽²⁾		36	mA
LP_D	Lowest Power Mode Dissipation (typical at 16.67 MHz)⁽³⁾		32	mA
LP_D	Lowest Power Mode Dissipation (typical at 50 MHz)⁽⁴⁾		1	mA

Notes: 1. The values shown are typical. The typical value varies as shown, based on how many IMP on-chip peripherals are enabled and the rate at which they are clocked.
2. LPREC = 0. Divider = 2.
3. LPREC = 1. Divider = 1024.
4. The stated frequency must be externally applied to EXTAL only after the IMP has been placed in the lowest power mode with LPREC = 1. The 68000 core is not specified to operate at this frequency, but the rest of the IMP is. In this configuration,the user does not divide the clock internally using the LPCD4-LPCD0 bits in the system control register.

TS68302 Features

• TS68000/TS68008 Microprocessor Core Supporting a 16- or 8-bit TS68000 Family
• System Integration Block Including:
Independent Direct Memory Access (IDMA) Controller
Interrupt Controller with Two Modes of Operation
Parallel Input/output (I/O) Ports, some with Interrupt Capability
On-chip Usable 1152 bytes of Dual-port Random-access Memory (RAM)
Three Timers, including a Watchdog Timer
Four Programmable Chip-select Lines with Wait-state Logic
Programmable Address Mapping of Dual-port RAM and IMP Registers
On-chip Clock Generator with an Output Clock Signal
System Control:
    System Control Register
    Bus Arbitration Logic with Low Interrupt Latency Support
    Hardware Watchdog for Monitoring Bus Activity
    Low Power (Standby) Modes
    Disable CPU Logic (TS68000)
    Freeze Control for Debugging Selected On-chip Peripherals
    DRAM Refresh Controller
• Communications Processor Including:
Main Controller (RISC Processor)
Three Full-duplex Serial Communication Controllers (SCCs)
Six Serial Direct Memory Access (SDMA) Channels Dedicated to the Three SCCs
Flexible Physical Interface Accessible by SCCs for Interchip Digital Link (IDL)General Circuit Interface (GCI, see note), Pulse Code Modulation (PCM), and Nonmultiplexed Serial Interface (NMSI) Operation
Serial Communication Port (SCP) for Synchronous Communication, Clock Rate up to 4.096 MHz
Serial Management Controllers (SMCs) for IDL and GCI Channels
• Frequency of Operation: 16.67 MHz
• Power Supply: 5 VDC ± 10%

TS68302 Connection Diagram

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