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TZA3012AHW, TZA3012HW, TZA3012HW/N1

Table of contents:
Info of TZA3012AHW
Info of TZA3012HW
Info of TZA3012HW/N1

TZA3012AHW, TZA3012HW, TZA3012HW/N1 Selling Leads, Datasheet

MFG:380 Package Cooled:NXP?HK D/C:IC-TEL*SONET*TZA3012

TZA3012AHW, TZA3012HW, TZA3012HW/N1 Picture

TZA3012AHW, TZA3012HW, TZA3012HW/N1 Datasheet download

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Part Number: TZA3012AHW

MFG: 380

Package Cooled: NXP?HK

D/C: IC-TEL*SONET*TZA3012

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TZA3012AHW General Description

The TZA3012AHW is a fully integrated optical network receiver containing a dual limiter, Data and Clock Recovery (DCR) and a demultiplexer with demultiplexing ratios 1:16, 1:10, 1:8 or 1:4.

The A-rate feature allows the IC to operate at any bit rate between 30 Mbits/s and 3.2 Gbits/s using a single reference frequency. The receiver supports loop modes with serial clock and data inputs and outputs. All clock signals are generated using a fractional N synthesizer with 10 Hz resolution giving a true, continuous rate operation.For full configuration flexibility, the receiver is programmable by pin or via the I²C-bus.

TZA3012AHW Maximum Ratings

SYMBOL	PARAMETER	MIN.	MAX.	UNIT
V_CCA,V_CCD V_CCO,V_DD	supply voltages	-0.5	+3.6	V
V_n	DC voltage on pins D00 to D15, D00Q to D15Q, POCLK, POCLKQ, FP, FPQ, PARITY, PARITYQ, PRSCLO and PRSCLOQ LOSTH1, LOSTH2 and RREF RSSI1 and RSSI2 UI, INSEL, WINSIZE, CS, SDA, SCL, DMXR0, DMXR1, ENBA, ENLOUTQ and ENLINQ LOS1, LOS2 and INWINDOW INT	V_CC- 0.5 -0.5 -0.5 -0.5 -0.5 -0.5	V_CC+ 0.5 V_CC+ 0.5 V_CC+ 0.5 V_CC+ 0.5 V_CC+ 0.5 V_CC+ 0.5	V V V V V V
I_n	input current on pins IN1, IN1Q, IN2 and IN2Q CREF, CREFQ, CLOOP, CLOOPQ, DLOOP and DLOOPQ INT	-30 -20 -2	+30 +20 +2	mA mA mA
T_amb	ambient temperature	-40	+85	°C
T_j	junction temperature	-	+125	°C
T_stg	storage temperature	-65	+150	°C

TZA3012AHW Features

· Single 3.3 V power supply
· I2C-bus and pin programmable fibre optic receiver.

Dual limiter features
· Dual limiting input with 12 mV sensitivity
· Received Signal Strength Indicator (RSSI)
· Loss Of Signal (LOS) indicator with threshold adjust
· Differential overvoltage protection.

Data and clock recovery features
· Supports SHD/SONET bit rates at 155.52, 622.08,2488.32 and 2666.06 Mbits/s (STM16/OC48 + FEC)
· Supports Gigabit Ethernet at 1250 and 3125 Mbits/s
· Supports Fibre Channel at 1062.5 and 2125 Mbits/s
· ITU-T compliant jitter tolerance
· Frequency lock indicator
· Stable clock signal when input data absent
· Outputs for recovered data and clock loop mode.

Demultiplexer features
· 1:16, 1:10, 1:8 or 1:4 demultiplexing ratio
· LVPECL or CML demultiplexer outputs
· Frame detection for SDH/SONET and GE frames
· Parity bit generation
· Loop mode inputs to demultiplexer.

Additional features with the I2C-bus
· A-rate^TM(1) supports any bit rate from 30 Mbits/s to 3.2 Gbits/s with one reference frequency
· Programmable frequency resolution of 10 Hz
· Four reference frequency ranges
· Adjustable swing of data, clock and parallel outputs
· Programmable polarity of all RF I/Os
· Exchangeable pin designations of RF clock with data for all I/Os for optimum connectivity
· Reversible pin designations of parallel data bus bits for optimum connectivity
· Slice level adjustment to improve Bit Error Rate (BER)
· Mute function for a forced logic 0 output state
· Programmable parity
· Programmable 32-bit frame detection.

TZA3012AHW Typical Application

· Any optical transmission system with bit rates between 30 Mbits/s and 3.2 Gbits/s
· Physical interface IC in receive channels
· Transponder applications
· Dense Wavelength Division Multiplexing (DWDM) systems.

TZA3012AHW Connection Diagram

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