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V54C36516G4VCT7, V54C365324V, V54C365404VD

Table of contents:
Info of V54C36516G4VCT7
Info of V54C365324V
Info of V54C365404VD

V54C36516G4VCT7, V54C365324V, V54C365404VD Selling Leads, Datasheet

MFG:MOSEL Package Cooled:Mosel D/C:9931

V54C36516G4VCT7, V54C365324V, V54C365404VD Picture

V54C36516G4VCT7, V54C365324V, V54C365404VD Datasheet download

Five Points

Part Number: V54C36516G4VCT7

MFG: MOSEL

Package Cooled: Mosel

D/C: 9931

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V54C365324V General Description

The V54C365324V is a 67,108, 864 bits synchronous high data rate DRAM organized as 4 x 524,288 words by 32 bits. The device is designed to comply with JEDEC standards set for synchronous DRAM products, both electrically and mechanically. Synchronous design allows precise cycle control with the system clock. The CAS latency, burst length and burst sequence must be programmed into device prior to access operation.

V54C365324V Maximum Ratings

Operating temperature range ................................................0 to 70 °C
Storage temperature range ..............................................-55 to 150 °C
Input/output voltage............................................... -0.3 to (V_CC+0.3) V
Power supply voltage ........................................................ -0.3 to 4.6 V
Power dissipation ............................................................................ 1 W
Data out current (short circuit) .................................................... 50 mA

V54C365324V Features

JEDEC Standard 3.3V Power Supply
The V54C365324V is ideally suited for high performance graphics peripheral applications
Single Pulsed RAS Interface
Programmable CAS Latency: 2, 3
All Inputs are sampled at the positive going edge of clock
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length: 1, 2, 4, 8 and Full Page for Sequential and 1, 2, 4, 8 for Interleave
DQM 0-3 for Byte Masking
Auto & Self Refresh
2K Refresh Cycles/32 ms
Burst Read with Single Write Operation

V54C365324V Connection Diagram

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