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V62C518256, V62C518256CC-70F, V62C518256L20T

Table of contents:
Info of V62C518256
Info of V62C518256CC-70F
Info of V62C518256L20T

V62C518256, V62C518256CC-70F, V62C518256L20T Selling Leads, Datasheet

MFG:VANGUARO Package Cooled:SOP28W D/C:2007+

V62C518256, V62C518256CC-70F, V62C518256L20T Picture

V62C518256, V62C518256CC-70F, V62C518256L20T Datasheet download

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Part Number: V62C518256

MFG: VANGUARO

Package Cooled: SOP28W

D/C: 2007+

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V62C518256 General Description

The V62C518256 is a 262,144-bit static random access memory organized as 32,768 words by 8 bits. It is built with MOSEL VITELIC's high performance CMOS process. Inputs and threestate outputs are TTL compatible and allow for direct interfacing with common system bus structures.

V62C518256 Maximum Ratings

Symbol	Parameter	Commercial	Industrial	Units
V_CC	Supply Voltage	-0.5 to +7	-0.5 to +7	V
V_N	Input Voltage	-0.5 to +7	-0.5 to +7	V
V_DQ	Input/Output Voltage Applied	V_CC+ 0.5	V_CC+ 0.5	V
T_BIAS	Temperature Under Bias	-10 to +125	-65 to +135
T_STG	Storage Temperature	-65 to +150	-65 to +150

NOTE:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage
    to the device. This is a stress rating only and functional operation of the device at these or any other
    conditions above those indicated in the operational sections of this specification is not implied. Exposure
    to absolute maximum rating conditions for extended periods may affect reliability.

V62C518256 Features

` High-speed: 35, 70 ns
` Ultra low DC operating current of 5mA (max.)
` Low Power Dissipation:
   TTL Standby: 3 mA (Max.)
   CMOS Standby: 20A (Max.)
` Fully static operation
` All inputs and outputs directly compatible
` Three state outputs
` Ultra low data retention current (V_CC= 2V)
` Single 5V±10% Power Supply
    28-pin TSOP (Standard)
    28-pin 600 mil PDIP
    28-pin 330 mil SOP (450 mil pin-to-pin)

V62C518256 Connection Diagram

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