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VT6421L, VT64KS4-55, VT6508

Table of contents:
Info of VT6421L
Info of VT64KS4-55
Info of VT6508

VT6421L, VT64KS4-55, VT6508 Selling Leads, Datasheet

MFG:VIA Package Cooled:TQFP-128 D/C:07+

VT6421L, VT64KS4-55, VT6508 Datasheet download

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Part Number: VT6421L

MFG: VIA

Package Cooled: TQFP-128

D/C: 07+

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VT6508 General Description

The VT6508 is a low-cost switch engine chip implementation of an 8 ports 10/100Mbps Ethernet switch system for IEEE 802.3 and IEEE 802.3u networks. Each port can be either auto-sensing or manually selected via EEPROM configuration to run at 10Mbps or 100Mbps speed rate, full or half duplex mode.

The VT6508 supports RMII (reduce MII) port interface. There are eight independent MACs within the VT6508 chip. The MAC controller controls the receiving, transmitting, and deferring of each individual port, and the MAC controller also provides framing, FCS checking, error handling, status indication and flow control function. It has wire-speed performance with forwarding rate of 148,810 packets/sec on each 100Mbps Ethernet port. The VT6508 can be configured via EEPROM or strapping only.

VT6508 Maximum Ratings

Parameter	Min	Max	Unit
Ambient operating temperature Case temperature Storage temperature	0 0 -55	70 100 125
Input voltage Output voltage (V_CC = 3.1 - 3.6V)	-0.5 -0.5	5.5 V_CC +0.5	Volts Volts

Note: Stress above the conditions listed may cause permanent damage to the device. Functional operation of this device should be restricted to the conditions described under operating conditions.

VT6508 Features

` Single chip 8 ports 10/100Mbps Ethernet switch controller
- Highly integrated single chip shared memory switch engine
- Supports 8 RMII (Reduced Media Independent Interface) ports
- Non-blocking layer 2 switch, 148,810 packets/sec on each 100Mbps Ethernet port
` Media Access Control (MAC)
- Dual 64-byte FIFO's per port for receiving and transmitting
` Auto-sensing 10/100Mbps media speed, full/half -duplex mode, and flow-control capability
` Two switching mechanisms
- Supports 'store and forward' switching with filtering CRC-bad packets
- Supports 'cut through' switching subject to long packets of length over 64 bytes
` Packet buffering
- Glueless 32-bit interface to SSRAM as a packet buffer pool
- 64 packet buffers for 32Kx32 SSRAM, 149 packet buffers for 64Kx32 SSRAM
- 1536 bytes for each packet buffer
` Storing control data (forwarding table and packet link entries) in external SSRAM
- Buffer status is stored in the internal free-buffer bit map registers
- Shared forwarding table of 2K entries (or 4K slots) to support multiple (up to 4K) Mac addresses per port
` Efficient address recognition, self learning, and auto-aging mechanism
- Two-slot hashing algorithm to prevent hash collision
- Two optional hashing algorithms, CRC-map and direct-map
` Advanced congestion control mechanism
- IEEE 802.3X compliant flow control for full duplex ports
- Backpressure for half duplex ports
- Drop control for full duplex ports without flow control capability
- Incorporating with the output private buffering scheme to prevent HOL (head of line) blocking
` Supports port mirroring (Sniffer feature)
` By-pass VLAN packets
`Support port-based trunking
- Support two individual trunk groups, each of 2 member ports
- Load balance according to DMAC address and source port number
`Support chip initialization through EEPROM or by strapping only
- Supports I2C EEPROM interface for customized configuration
- Supports LED serial-out in the strapping-only initialization mode
`50MHz internal reference clock rate
`83~100MHz SSRAM clock rate, typically 83MHz
`Single +3.3V supply, 0.3mm TSMC CMOS technology
`128-pin PQFP package

VT6508 Connection Diagram

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