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VT6510B, VT6516, VT6518C

Table of contents:
Info of VT6510B
Info of VT6516
Info of VT6518C

VT6510B, VT6516, VT6518C Selling Leads, Datasheet

MFG:VITESSE Package Cooled:QFP D/C:246

VT6510B, VT6516, VT6518C Datasheet download

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Part Number: VT6510B

MFG: VITESSE

Package Cooled: QFP

D/C: 246

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VT6516 General Description

The VT6516 is a switch engine chip implementation of a 16 ports 10/100M Ethernet switch system for IEEE 802.3 and IEEE 802.3u network. Each of individual port can be either auto-sensing or manually selected to run at 10Mbps or 100Mbps speed rate and under full or half duplex mode.

There are sixteen independent MACs within the VT6516 chip. The MAC controller controls the receiving, transmitting, and deferring of each individual port, and the MAC controller also provides framing, FCS checking, error handling, status indication and flow control function.

The VT6516 10/100M N-way switch port IC is wire-speed performance and low-cost packet switch; it can forward up to 148,810 packets/sec on each Ethernet port. The VT6516 support 12 ports MII or 16 ports RMII (reduce MII) interface for network interface,

The VT6516 used the simple 8/16 bits ISA-like interface to support initiation, expansion and management. The system CPU can access various registers inside VT6516 through a simple ISA-like CPU interface. The CPU can configure the switch by writing into the appropriate registers, or retrieve the status of the switch by reading the corresponding registers. The CPU can also access the register of external transceiver (PHY) device through the CPU interface.

The VT6516 supports new features including port based VLAN , 802.3X flow control, and the VT6516 also support the sniffer function to monitor network traffic in special ports.

VT6516 Maximum Ratings

Parameter	Min	Max	Unit
Ambient operating temperature Case temperature Storage temperature Input voltage Output voltage (V_CC = 3.1 - 3.6V)	0 0 -55 -0.5 -0.5	70 100 125 5.5 V_CC + 0.5	Volts Volts

VT6516 Features

Single chip 16/12 ports 10/100M Ethernet switch controller
- Highly integrated single chip shared memory switch engine
- With option for 16 RMII (Reduced Media Independent Interface) ports or 12 MII (Media Independent Interface) ports
- Non-blocking layer 2 switch, 148,810 packets/sec on each 100Mbps Ethernet port
Media Access Control (MAC)
- Dual 192-bytes FIFO's of receive and transmit for each port
- CRC generator for outgoing packets from CPU port
- IEEE 802.3X compliant flow control for full duplex ports
- Backpressure for half duplex ports
Two switching mechanisms
- Supports 'store and forward' switching without forwarding CRC-bad packets
- Supports 'cut through' switching subject to long packets of length over 290 bytes for 100Mbps ports or of length over 98 bytes for 10Mbps ports
Packet buffering
- Glueless 64-bit interface to SDRAM as a packet buffer pool with size from 2M bytes (SGRAM) to 512 M bytes
- 1536 bytes for each packet buffer
External 32 bits SSRAM interface for forwarding table and memory link table
- Link list structure initialized by software
- 2K up to 32K unicast/multicast addresses table entries with VLAN information
- Supports static entries for upper-layer multicast protocols, e.g. IGMP
Advanced address recognition
- Layer 2 MAC address recognition engine to enable wire-speed forwarding rate
- Self learning mechanism
- Supports multiple MAC address per-port from 2K up to 32K unicast/multicast addresses
Switch management support
- Supports port mirroring (Sniffer feature)
- Supports spanning tree algorithm
- Supports CPU direct access to SDRAM and SSRAM
- Supports five statistical counters in each port
Supports I2C EEPROM interface for customized configuration
Support port-grouping VLAN
- Configurable server ports belonging to multiple VLAN groups
Support port-based trunking
- Three types of trunk grouping: one trunk group with 2 or 4 ports, two trunk groups each with 2 ports
- Load balance according to MAC address and port number
CPU interface VIA 8/16 bits ISA-like interface
- Chip initialization, auto-aging and spanning tree algorithm support by firmware
- Auto-sensing 10/100M media speed, duplex mode, and flow-control capability by firmware
50MHz internal reference clock rate
50~100MHz SDRAM clock rate, typically 83MHz
50~100MHz SSRAM clock rate, typically 83MHz
Single +3.3V supply, 0.3mm standard CMOS technology
476 ball BGA package

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