X25165, X25170, X25170 /AE/AF/I Selling Leads, Datasheet
MFG:XICOR Package Cooled:XICOR D/C:9945
X25165, X25170, X25170 /AE/AF/I Datasheet download

Part Number: X25165
MFG: XICOR
Package Cooled: XICOR
D/C: 9945
MFG:XICOR Package Cooled:XICOR D/C:9945
X25165, X25170, X25170 /AE/AF/I Datasheet download

MFG: XICOR
Package Cooled: XICOR
D/C: 9945
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Datasheet: X25165
File Size: 78630 KB
Manufacturer: XICOR [Xicor Inc.]
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PDF/DataSheet Download
Datasheet: X25170S8IG-2.5
File Size: 135119 KB
Manufacturer: ICMIC [IC MICROSYSTEMS]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: X25
File Size: 60579 KB
Manufacturer:
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These devices combine three popular functions, Watchdog Timer, Supply Voltage Supervision, and Serial E2PROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability.
The Watchdog Timer provides an independent protection mechanism for microcontrollers. During a system failure, the device will respond with a RESET/RESET signal after a selectable time-out interval. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power.
The user's system is protected from low voltage conditions by the device's low Vcc detection circuitry. When Vcc falls below the minimum Vcc trip point, the system is reset. RESET/RESET is asserted until Vcc returns to proper operating levels and stabilizes.
The memory portion of the device is a CMOS Serial E2PROM array with Xicor's Block LockTM Protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.
The device utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years.

The X25170 is a CMOS 16384-bit serial E2PROM, internally organized as 2K x 8. The X25170 features a Serial Peripheral Interface (SPI) and software protocol, allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus.
The X25170 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25170 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25170 (disabling all write attempts to the status register), thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory.
The X25170 utilizes Xicor's proprietary Direct Write cell,providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.

