YSS901-F, YSS902, YSS902-F00 Selling Leads, Datasheet
MFG:120 Package Cooled:NA D/C:NA
YSS901-F, YSS902, YSS902-F00 Datasheet download
Part Number: YSS901-F
MFG: 120
Package Cooled: NA
D/C: NA
MFG:120 Package Cooled:NA D/C:NA
YSS901-F, YSS902, YSS902-F00 Datasheet download
MFG: 120
Package Cooled: NA
D/C: NA
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Datasheet: yss205
File Size: 920559 KB
Manufacturer:
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PDF/DataSheet Download
Datasheet: YSS902
File Size: 612097 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: yss205
File Size: 920559 KB
Manufacturer:
Download : Click here to Download
The YSS902 is one chip LSI consisting of two built-in DSP's ; Dolby Digital (AC-3) / Pro Logic (Main DSP) and a sound processing DSP (Sub DSP). Sub DSP is capable of realizing various sound fields, such as virtual surround, by down-loading the program and coefficient.
Parameter | Symbol | Min. | Max. | Unit |
Power Supply Voltage | VDD1 VDD2, AVDD |
Vss-0.5 Vss-0.5 |
Vss+7.0 VSS+4.6 |
V V |
Input Voltage | VI | Vss-0.5 | VDD1+0.5 | V |
Storage Temperature | Tstg | -50 | 125 |
·Dolby Digital 5.1 channel full decode.
·24 bit DSP. (Group-A Dolby Digital decoder)
·No external memory is required. (Memory for center and surround channel delay is included)
·Possible to decode multi-language encoded data. (possible to decode based on data-stream-number)
·AC-3 karaoke mode.
·Original compression mode as well as four compression modes recommended by Dolby.
·Dolby Digital decoding latency is fixed to two audio blocks (512 samples).
·Included de-emphasis filter.
·Pro Logic decoding for Dolby Digital 2 channels decoded signal as well as ordinary PCM.
·High performance 25 MIPS programmable DSP suitable for a variety of sound field processing such as original surround, filtering, virtual surround etc.
·Up to 1.36 second delay time is capable when used with an external 1Mbit SRAM. (at fs= 48 kHz)
·Reads Dolby Digital decode information through the microprocessor interface.
·Provide total sixteen I/O ports.
·Possible to connect most of SPDIF receivers, A/D and D/A converters, by setting I/O data interface format.
·Has a built-in PLL oscillation circuit to generates its own operating clock.
·Internal operating clock is 25MHz.
·Supply Voltage: 3.3v for core logic. 5v for I/Os.
·Power saving mode.
·Si-gate CMOS process.
·100 QFP.(YSS902-F)