Z85C30, Z85C3006CMB 5962-8868901QA, Z85C3006CMB/883 Selling Leads, Datasheet
MFG:ZILOG Package Cooled:DIP
Z85C30, Z85C3006CMB 5962-8868901QA, Z85C3006CMB/883 Datasheet download
Part Number: Z85C30
MFG: ZILOG
Package Cooled: DIP
D/C:
Position: Home > DataSheet > Index Z > Z85 Series > Z85C30, Z85C3006CMB 5962-8868901QA, Z85C3006CMB/883
Z85C30, Z85C3006CMB 5962-8868901QA, Z85C3006CMB/883
- Table of contents:
Info of Z85C30
Info of Z85C3006CMB 5962-8868901QA
Info of Z85C3006CMB/883
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About Z85C30
PDF/DataSheet Download
Datasheet: Z85C30
File Size: 901120 KB
Manufacturer: ZILOG [Zilog, Inc.]
Download : Click here to Download
About Z85230
PDF/DataSheet Download
Datasheet: Z85230
File Size: 3278174 KB
Manufacturer: ZILOG [Zilog, Inc.]
Download : Click here to Download
About Z85230
PDF/DataSheet Download
Datasheet: Z85230
File Size: 3278174 KB
Manufacturer: ZILOG [Zilog, Inc.]
Download : Click here to Download
Z85C30 Features
` New programmable WR7' (write register 7 prime) to enable new features.
` Improvements to support SDLC mode of synchronous communication:
Improved functionality to ease sending back-to back frames
Automatic SDLC opening Flag transmission*
Automatic Tx Underrun/EOM Latch reset in SDLC mode*
Automatic /RTS deactivation*
TxD pin forced "H" in SDLC NRZI mode after closing flag*
Complete CRC reception*
Improved response to Abort sequence in status FIFO
Automatic Tx CRC generator preset/reset
Extended read for write registers*
Write data setup timing improvement
` Improved AC timing:
Three to 3.5 PCLK access recovery time.
Programmable /DTR//REQ timing*
Elimination of write data to falling edge of /WR setup time requirement
Reduced /INT timing
` Other features include:
Extended read function to read back the written value to the write registers*
Latching RR0 during read
RR0, bit D7 and RR10, bit D6 now has reset defaultvalue.
` Deeper transmit FIFO (4 bytes)
` Deeper receive FIFO (8 bytes)
` Programmable FIFO interrupt and DMA request level
` Seven enhancements to improve SDLC link layer supports:
Automatic transmission of the opening flag
Automatic reset of Tx Underrun/EOM latch
Deactivation of /RTS pin after closing flag
Automatic CRC generator preset
Complete CRC reception
TxD pin automatically forced high with NRZI encoding when using mark idle
Status FIFO handles better frames with an ABORT
Receive FIFO automatically unlocked for special receive interrupts when using the SDLC status FIFO
` Delayed bus latching for easier microprocessor interface
` New programmable features added with Write Register7' (WR seven prime)
` Write registers 3, 4, 5 and 10 are now readable
` Read register 0 latched during access
` DPLL counter output available as jitter-free transmitter clock source
` Enhanced /DTR, /RTS deactivation timing
` Improvements to support SDLC mode of synchronous communication:
Improved functionality to ease sending back-to back frames
Automatic SDLC opening Flag transmission*
Automatic Tx Underrun/EOM Latch reset in SDLC mode*
Automatic /RTS deactivation*
TxD pin forced "H" in SDLC NRZI mode after closing flag*
Complete CRC reception*
Improved response to Abort sequence in status FIFO
Automatic Tx CRC generator preset/reset
Extended read for write registers*
Write data setup timing improvement
` Improved AC timing:
Three to 3.5 PCLK access recovery time.
Programmable /DTR//REQ timing*
Elimination of write data to falling edge of /WR setup time requirement
Reduced /INT timing
` Other features include:
Extended read function to read back the written value to the write registers*
Latching RR0 during read
RR0, bit D7 and RR10, bit D6 now has reset defaultvalue.
` Deeper transmit FIFO (4 bytes)
` Deeper receive FIFO (8 bytes)
` Programmable FIFO interrupt and DMA request level
` Seven enhancements to improve SDLC link layer supports:
Automatic transmission of the opening flag
Automatic reset of Tx Underrun/EOM latch
Deactivation of /RTS pin after closing flag
Automatic CRC generator preset
Complete CRC reception
TxD pin automatically forced high with NRZI encoding when using mark idle
Status FIFO handles better frames with an ABORT
Receive FIFO automatically unlocked for special receive interrupts when using the SDLC status FIFO
` Delayed bus latching for easier microprocessor interface
` New programmable features added with Write Register7' (WR seven prime)
` Write registers 3, 4, 5 and 10 are now readable
` Read register 0 latched during access
` DPLL counter output available as jitter-free transmitter clock source
` Enhanced /DTR, /RTS deactivation timing
Z85C30 Typical Application
Q. Which of the following is a benefit from deeper FIFOs offered by the ESCC?
a. More CPU bandwidths available for other system tasks
b. Can support faster data rates on each channel
c. Can support more channels for the same CPU
d. All of the above
A. (d) (a), (b) and (c) are consequences of reduction in interrupt frequency that allows more horsepower to be
delivered from the CPU.
Q. Which of the following CRC polynomials is supported in ESCC?
a. CRC-16
b. CRC-32
c. (CRC-CCITT
d. (a) and (c)
e. (b) and (c)
A. (d) CRC-32 is not supported in ESCC.
Q. How long does it usually take for the customer to migrate from SCC to ESCC in order to take the advantage of the FIFO?
a. Less than 3 month
b. About 6 month
c. About a year
A. (a) Since the ESCC is a drop-in replacement to the SCC and using the deeper FIFO only requires minimal efforts.
Q. Which of the following is an applications support the tool for ESCC:
a. Sealevel Board
b. (Electronic Programmers Manual
c. Application Note "Boost Your System Performance Using the Zilog ESCC""
d. All of the above
A. (d)
Q. Which of the following is a target application for the ESCC?
a. AppleTalk-LocalTalk Peripherals
b. X.25 Packet Switches
c. SNA connectivity products
d. All of the above
A. (d) ESCC could support the data rate and protocol required in the above applications
a. More CPU bandwidths available for other system tasks
b. Can support faster data rates on each channel
c. Can support more channels for the same CPU
d. All of the above
A. (d) (a), (b) and (c) are consequences of reduction in interrupt frequency that allows more horsepower to be
delivered from the CPU.
Q. Which of the following CRC polynomials is supported in ESCC?
a. CRC-16
b. CRC-32
c. (CRC-CCITT
d. (a) and (c)
e. (b) and (c)
A. (d) CRC-32 is not supported in ESCC.
Q. How long does it usually take for the customer to migrate from SCC to ESCC in order to take the advantage of the FIFO?
a. Less than 3 month
b. About 6 month
c. About a year
A. (a) Since the ESCC is a drop-in replacement to the SCC and using the deeper FIFO only requires minimal efforts.
Q. Which of the following is an applications support the tool for ESCC:
a. Sealevel Board
b. (Electronic Programmers Manual
c. Application Note "Boost Your System Performance Using the Zilog ESCC""
d. All of the above
A. (d)
Q. Which of the following is a target application for the ESCC?
a. AppleTalk-LocalTalk Peripherals
b. X.25 Packet Switches
c. SNA connectivity products
d. All of the above
A. (d) ESCC could support the data rate and protocol required in the above applications
Z85C30 Connection Diagram
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