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6-5179010-0, 6518, 65182-001LF

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MFG:FCI  Category:Connectors  Package Cooled:SMD  D/C:06

6-5179010-0, 6518, 65182-001LF Picture

6-5179010-0, 6518, 65182-001LF Datasheet download

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Part Number: 6-5179010-0

Category: Connectors

MFG: FCI

Package Cooled: SMD

D/C: 06

Description: BP LATCH LF

 

 
 
 
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  • 6-534206-0

  • Vendor: Amphenol D/C: 09+& Qty: 22 Note: new and orginal  Adddate: 2019-08-21
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  • golden gate electronics Ltd   China
    Contact: Ms.Amy   MSN:e-com@agoldgate.com
    Tel: 0086-755-82998161
    Fax: 0086-755-83742611
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  • 65119

  • D/C: 04+& Qty: ST  Adddate: 2019-08-21
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  • Action Dynamic   China
    Contact: Ms.AdaHuang   MSN:dn0755@hotmail.com
    Tel: 86-0755-83957495
    Fax: 86-0755-83987630
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  • 65129GE

  • Vendor: Infineon Qty: 25,000  Adddate: 2019-08-21
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  • RSI   United
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  • 65119

  • D/C: 04+& Qty: ST  Adddate: 2019-08-21
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  • Action Dynamic   China
    Contact: Ms.AdaHuang   MSN:dn0755@hotmail.com
    Tel: 86-0755-83957495
    Fax: 86-0755-83987630
    (6)
  • 65129GE

  • Vendor: Infineon Qty: 25,000  Adddate: 2019-08-21
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  • RSI   United
    Contact: Mr.John Jardine  
    Tel: 011-310-325-2955
    Fax: 011-310-325-1738
    (33)

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6518 General Description

The Galvantech Synchronous Burst SRAM family mploys high-speed, low power CMOS designs using dvanced triple-layer polysilicon, double-layer metal echnology. Each memory cell consists of four transistors and wo high valued resistors.

The GVT71256F18 SRAM integrates 262,144x18 RAM cells with advanced synchronous peripheral circuitry nd a 2-bit counter for internal burst operation. All ynchronous inputs are gated by registers controlled by a ositive-edge-triggered clock input (CLK). The synchronous nputs include all addresses, all data inputs, address-pipelining hip enable (CE#), depth-expansion chip enables (CE2# and E2), burst control inputs (ADSC#, ADSP#, and ADV#),write enables (WEL#, WEH#, and BWE#), and global write GW#).

Asynchronous inputs include the output enable (OE#) nd burst mode control (MODE). The data outputs (Q), nabled by OE#, are also asynchronous.

ddresses and chip enables are registered with either ddress status processor (ADSP#) or address status controller ADSC#) input pins. Subsequent burst addresses can be nternally generated as controlled by the burst advance pin ADV#).

Address, data inputs, and write controls are registered onchip o initiate self-timed WRITE cycle. WRITE cycles can e one to four bytes wide as controlled by the write control nputs. Individual byte write allows individual byte to be ritten. WEL# controls DQ1-DQ8 and DQP1. WEH# ontrols DQ9-DQ16 and DQP2. WEL#, and WEH# can be ctive only with BWE# being LOW. GW# being LOW causes ll bytes to be written. WRITE pass-through capability allows ritten data available at the output for the immediately next EAD cycle. This device also incorporates pipelined enable ircuit for easy depth expansion without penalizing system erformance.

The GVT71256F18 operates from a +3.3V core power upply and all outputs operate on a +2.5V supply. All inputs nd outputs are JEDEC standard JESD8-5 compatible. The evice is ideally suited for 486, PentiumTM, 680x0, and owerPCTM systems and for systems that are benefited from a ide synchronous data bus.

6518 Maximum Ratings

Voltage on VCC Supply Relative to VSS.......     -0.5V to +4.6V
VIN ..........................................................  -0.5V to VCC+0.5V
Storage Temperature (plastic) .......................-55oC to +150o
Junction Temperature ...................................................+150o
Power Dissipation ...........................................................1.0W
Short Circuit Output Current ..........................................50mA
*Stresses greater than those listed uunder "Absolute Maximum atings" may cause permanent damage to the device.This is a stress ating only and functional operation of the device at these or any ther conditions above those indicated in the operational sections of his specification is not implied. Exposure to absolute maximum ating conditions for extended periods may affect reliability.

6518 Features

• Fast access times: 3.5, 3.8, and 4.0ns
• Fast clock speed: 166, 150, 133, and 117MHz
• Provide high performance 3-1-1-1 access rate
• Fast OE# access times: 3.5ns and 3.8ns
• Optimal for performance (two cycle chip deselect, depth xpansion without wait state)
• 3.3V -5% and +10% core power supply
• 2.5V or 3.3V I/O supply
• 5V tolerant inputs except I/O's
• Clamp diodes to VSSQ at all inputs and outputs
• Common data inputs and data outputs
• BYTE WRITE ENABLE and GLOBAL WRITE control
• Three chip enables for depth expansion and address ipeline
• Address, data and control registers
• Internally self-timed WRITE CYCLE
• Burst control pins (interleaved or linear burst sequence)
• Automatic power-down for portable applications
• High density, high speed packages

6518 Connection Diagram

65182-001LF Parameters

Technical/Catalog Information65182-001LF
VendorFCI
CategoryConnectors
Accessory TypeLatch
For Use With/Related Products-
SpecificationsLocking
Lead Free StatusLead Free
RoHS StatusRoHS Compliant
Other Names 65182 001LF
65182001LF

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