82801BA, 82801BAM, 82801CAM Selling Leads, Datasheet
MFG:INTEL Package Cooled:BGA D/C:New
82801BA, 82801BAM, 82801CAM Datasheet download
Part Number: 82801BA
MFG: INTEL
Package Cooled: BGA
D/C: New
82801BA, 82801BAM, 82801CAM
- Table of contents:
Info of 82801BA
Info of 82801BAM
Info of 82801CAM
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About 82801BA
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Datasheet: 82801BA
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About 82801AA
PDF/DataSheet Download
Datasheet: 82801AA
File Size: 2191976 KB
Manufacturer: INTEL [Intel Corporation]
Download : Click here to Download
About 82801AA
PDF/DataSheet Download
Datasheet: 82801AA
File Size: 2191976 KB
Manufacturer: INTEL [Intel Corporation]
Download : Click here to Download
82801CAM General Description
This section provides a detailed description of each signal. The signals are arranged in functionalgroups according to their associated interface.
The "#" symbol at the end of the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present, the signal is asserted when at the high voltage level.
82801CAM Maximum Ratings
Case Temperature under Bias = 0 to +108
Storage Temperature = -55 to +150
Voltage on Any 3.3 V Pin with Respect to Ground = -0.5 to Vcc + 0.3 V
Voltage on Any 5 V Tolerant Pin with Respect to Ground (VREF=5V) = -0.5 to VREF + 0.3 V
1.8 V Supply Voltage with Respect to Vss = -0.5 to +2.7 V
3.3 V Supply Voltage with Respect to Vss = -0.5 to +4.6 V
5.0 V Supply Voltage (Vref) with Respect to Vss = -0.5 to +5.5 V
Storage Temperature = -55 to +150
Voltage on Any 3.3 V Pin with Respect to Ground = -0.5 to Vcc + 0.3 V
Voltage on Any 5 V Tolerant Pin with Respect to Ground (VREF=5V) = -0.5 to VREF + 0.3 V
1.8 V Supply Voltage with Respect to Vss = -0.5 to +2.7 V
3.3 V Supply Voltage with Respect to Vss = -0.5 to +4.6 V
5.0 V Supply Voltage (Vref) with Respect to Vss = -0.5 to +5.5 V
82801CAM Features
PCI Bus I/F
- Supports PCI Rev 2.2 Specification at 33 MHz
- 133 MByte/sec maximum throughput
- Supports up to 6 master devices on PCI
- One PCI REQ/GNT pair can be given higher arbitration priority (intended for external IEEE 1394 host controller)
Integrated LAN Controller
- WfM 2.0 Compliant
- Interface to discrete LAN Connect component
- 10/100 Mbit/sec Ethernet support
- 1 Mbit/sec HomePNA* support
Integrated IDE Controller
- New: Supports "Native Mode" Register and Interrupt support
- Independent timing of up to 4 drives, with separate IDE connections for Primary and Secondary cables
- Ultra ATA/100/66/33, BMIDE and PIO modes
- Tri-state modes to enable mobile swap bay
USB
- New: Includes 3 UHCI Host Controllers,increasing the number of external ports to six
- Supports wake-up from sleeping states S1-S4
- Supports legacy Keyboard/Mouse software
AC'97 Link for Audio and Telephony CODECs
- Audio Codec '97, Revision 2.2 compliant
- Independent bus master logic for 5 channels (PCM In/Out, Mic Input, Modem In/Out)
- Separate independent PCI functions for Audio and Modem
- Support for up to six channels of PCM audio output (full AC3 decode)
- Supports wake-up events
Interrupt Controller
- Support up to 8 PCI interrupt pins
- Supports PCI 2.2 Message Signaled Interrupts
- Two cascaded 82C59 with 15 interrupts
- Integrated I/O APIC capability with 24 interrupts
- Supports Serial Interrupt Protocol
- Supports Processor System Bus interrupt delivery
1.8 V operation with 3.3 V I/O
- 5V tolerant buffers on IDE, PCI, USB Overcurrent and Legacy signals
Timers Based on 82C54
- System timer, Refresh request, Speaker tone output
External Glue Integration
- Integrated Pull-up, Pull-down and Series Termination resistors on IDE, CPU I/F, and USB
Power Management Logic
- ACPI 1.0 compliant
- ACPI-defined power states C1-C4, S1, S3-S5
- ACPI Power Management Timer
- Support for "Intel® SpeedStep™ Technology" CPU power control
- New: Support for "Deeper Sleep" power state
- PCI CLKRUN# and PME# support
- SMI# generation
- All registers readable/restorable for proper resume from 0 V suspend states
- Support for APM-based legacy power management for non-ACPI implementations
Firmware Hub (FWH) I/F supports BIOS Memory size up to 8 MB
Low Pin count (LPC) I/F
- Allows connection of legacy ISA and X-Bus devices such as Super I/O
- Supports two Master/DMA devices.
Enhanced DMA Controller
- Two cascaded 8237 DMA controllers
- PCI DMA: Supports PC/PCI-Includes two PC/PCI REQ#/GNT# pairs
- Supports LPC DMA
- Supports DMA Collection Buffer to provide Type-F DMA performance for all DMA channels
Real-Time Clock
- 256-byte battery-backed CMOS RAM
System TCO Reduction Circuits
- Timers to generate SMI# and Reset upon detection of system hang
- Timers to detect improper processor reset
- Integrated processor frequency strap logic
- New: Supports ability to disable external devices
SMBus
- Host interface allows processor to communicate via SMBus
- Slave interface allows an external Microcontroller to access system resources
- Compatible with most 2-Wire components that are also I2C* compatible
- New: Supports SMBus 2.0 Specification
Power Management Logic
- ACPI 1.0 compliant
- ACPI-defined power states C1-C4, S1, S3-S5
- ACPI Power Management Timer
- Support for "Intel® SpeedStep™ Technology" CPU power control
- New: Support for "Deeper Sleep" power state
- PCI CLKRUN# and PME# support
- SMI# generation
- All registers readable/restorable for proper resume from 0 V suspend states
- Support for APM-based legacy power management for non-ACPI implementations
Firmware Hub (FWH) I/F supports BIOS Memory size up to 8 MB
Low Pin count (LPC) I/F
- Allows connection of legacy ISA and X-Bus devices such as Super I/O
- Supports two Master/DMA devices.
Enhanced DMA Controller
- Two cascaded 8237 DMA controllers
- PCI DMA: Supports PC/PCI-Includes two PC/PCI REQ#/GNT# pairs
- Supports LPC DMA
- Supports DMA Collection Buffer to provide Type-F DMA performance for all DMA channels
Real-Time Clock
- 256-byte battery-backed CMOS RAM
System TCO Reduction Circuits
- Timers to generate SMI# and Reset upon detection of system hang
- Timers to detect improper processor reset
- Integrated processor frequency strap logic
- New: Supports ability to disable external devices
SMBus
- Host interface allows processor to communicate via SMBus
- Slave interface allows an external Microcontroller to access system resources
- Compatible with most 2-Wire components that are also I2C* compatible
- New: Supports SMBus 2.0 Specification
GPIO
- TTL, Open-Drain, Inversion
New: Package 31x31 mm 421 BGA GPIO
- TTL, Open-Drain, Inversion
New: Package 31x31 mm 421 BGA
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