82845GES, 82845GV, 82845MP Selling Leads, Datasheet
MFG:BGA Package Cooled:INTEL
82845GES, 82845GV, 82845MP Datasheet download
Part Number: 82845GES
MFG: BGA
Package Cooled: INTEL
D/C:
82845GES, 82845GV, 82845MP
- Table of contents:
Info of 82845GES
Info of 82845GV
Info of 82845MP
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About 82801AA
PDF/DataSheet Download
Datasheet: 82801AA
File Size: 2191976 KB
Manufacturer: INTEL [Intel Corporation]
Download : Click here to Download
About 82845GV
PDF/DataSheet Download
Datasheet: 82845GV
File Size: 3061789 KB
Manufacturer: INTEL [Intel Corporation]
Download : Click here to Download
About 82845MP
PDF/DataSheet Download
Datasheet: 82845MP
File Size: 1441774 KB
Manufacturer: INTEL [Intel Corporation]
Download : Click here to Download
82845MP Maximum Ratings
|
Symbol |
Parameter |
Min |
Max |
Unit |
|
Tdie |
Die Temperature under Bias |
0 |
98 |
|
| Tdie | Die Temperature under Bias (without heatsink) | 0 | 104 | |
|
Tstorage |
Storage Temperature |
-55 |
150 |
|
|
VCC1_5 |
1.5 V Supply Voltage with respect to Vss |
-0.72 |
2.69 |
V |
| VCC1_8 | 1.8 V Supply Voltage with respect to Vss | -0.88 | 2.5 | |
|
VCCSM |
2.5 V DDR Supply Voltage with respect to Vss |
-3.60 |
6.3 |
V |
|
VTT |
AGTL+ buffer DC input voltage with respect to Vss |
-0.55 |
2.3 |
V |
|
VIL, VIH |
Voltage on 2.5 V DDR tolerant input pins with |
-3.60 |
6.30 |
V |
82845MP Features
Processor/Host Bus Support
-Supports the Mobile Intel Pentium 4 Processor-M CPU
-Supports the Intel Pentium(C)4 processor subset of the Enhanced Mode Scaleable Bus Protocol
-2x Address, 4x Data
-Mobile Intel Pentium 4 Processor-M System Bus interrupt delivery
-Supports system bus at 400 MT/s (100 MHz)
-Supports host bus Dynamic Bus Inversion (DBI)
-Supports 32-bit host bus addressing
-12 deep In-Order Queue
-AGTL+ bus driver technology with integrated AGTL termination resistors
Memory System
-Directly supports one DDR channel, 64b wide (72b with ECC).
-Supports 200 and 266-MHz DDR compliant devices (845MZ supports 200 MHz DDR only)
-Supports 64-Mb, 128-Mb, 256-Mb and 512-Mb technologies for x16 devices and x8 devices.
-All supported devices have 4 banks
- Configurable optional ECC operation (single bit Error Correction and multiple bit Error Detection)
- Supports up to 16 simultaneous open pages
-Supports page sizes of 2 KB, 4 KB, 8 KB, and 16 KB. Page size is individually selected for every row.
- Thermal throttling scheme to selectively throttle reads and/or writes. Throttling can be triggered by preset read/write bandwidth limits.
- Max of 2 double-sided (4 rows populated) with unbuffered PC2100 DDR (with or without ECC) SO-DIMMs (845MZ supports only 200-MHz DDR).
-Largest memory supported is 1 GB (845MZ supports only up to 512 MB).
System Interrupts
-Supports only System Bus interrupt delivery mechanism
-Supports interrupts signaled as upstream Memory Writes from AGP/PCI (PCI semantics only) and hub interface
- MSI direct to the System Bus
- Supports peer MSI between hub interface and AGP
- Provides redirection for IPI and upstream interrupts to the System Bus
Accelerated Graphics Port (AGP) Interface
-Supports a single AGP device (either a connector or on the motherboard)
-AGP Support
-Supports AGP 2.0 including 1x, 2x, and 4x AGP data transfers and 2x/4x Fast Write protocol
-Supports only 1.5-V AGP electricals
-32 deep AGP request queue
-PCI semantic (FRAME# initiated) accesses to DRAM are snooped
-High priority access support
- Hierarchical PCI configuration mechanism
-Delayed transaction support for AGP-to-DRAM FRAME# semantic reads that can not be serviced immediately
-32-bit upstream address support for inbound AGP and PCI cycles
-32-bit downstream address support for outbound PCI and Fast Write cycles
-AGP Busy/Stop Protocol
-AGP Clamping and Sense Amp Control
Hub Interface to ICH3-M
- 266-MB/s, point-to-point hub interface to ICH3-M
-66-MHz base clock
- Supports the following traffic types to the ICH3-M
-Hub interface-to-AGP memory writes
- Hub interface-to-DRAM
- CPU-to-hub interface
-Messaging
- MSI Interrupt messages
- Power Management state change
- SMI, SCI and SERR error indication
Power Management
-SMRAM space remapping to A0000h (128 KB)
-Supports extended SMRAM space above 256 MB, additional 128K/256K/512K TSEG from Top of Memory, cacheable (cacheability controlled by CPU)
- APM Rev 1.2 compliant power management
-Suspend to System Memory
- ACPI 2.0 Support
-Intel SpeedStep(TM) technology support
- Cache coherency with CPU in sleep mode
- Dynamic Memory Power-down
Package
-Package options
-593-pin FC-BGA (37.5 x 37.5 mm)
-Supports the Mobile Intel Pentium 4 Processor-M CPU
-Supports the Intel Pentium(C)4 processor subset of the Enhanced Mode Scaleable Bus Protocol
-2x Address, 4x Data
-Mobile Intel Pentium 4 Processor-M System Bus interrupt delivery
-Supports system bus at 400 MT/s (100 MHz)
-Supports host bus Dynamic Bus Inversion (DBI)
-Supports 32-bit host bus addressing
-12 deep In-Order Queue
-AGTL+ bus driver technology with integrated AGTL termination resistors
Memory System
-Directly supports one DDR channel, 64b wide (72b with ECC).
-Supports 200 and 266-MHz DDR compliant devices (845MZ supports 200 MHz DDR only)
-Supports 64-Mb, 128-Mb, 256-Mb and 512-Mb technologies for x16 devices and x8 devices.
-All supported devices have 4 banks
- Configurable optional ECC operation (single bit Error Correction and multiple bit Error Detection)
- Supports up to 16 simultaneous open pages
-Supports page sizes of 2 KB, 4 KB, 8 KB, and 16 KB. Page size is individually selected for every row.
- Thermal throttling scheme to selectively throttle reads and/or writes. Throttling can be triggered by preset read/write bandwidth limits.
- Max of 2 double-sided (4 rows populated) with unbuffered PC2100 DDR (with or without ECC) SO-DIMMs (845MZ supports only 200-MHz DDR).
-Largest memory supported is 1 GB (845MZ supports only up to 512 MB).
System Interrupts
-Supports only System Bus interrupt delivery mechanism
-Supports interrupts signaled as upstream Memory Writes from AGP/PCI (PCI semantics only) and hub interface
- MSI direct to the System Bus
- Supports peer MSI between hub interface and AGP
- Provides redirection for IPI and upstream interrupts to the System Bus
Accelerated Graphics Port (AGP) Interface
-Supports a single AGP device (either a connector or on the motherboard)
-AGP Support
-Supports AGP 2.0 including 1x, 2x, and 4x AGP data transfers and 2x/4x Fast Write protocol
-Supports only 1.5-V AGP electricals
-32 deep AGP request queue
-PCI semantic (FRAME# initiated) accesses to DRAM are snooped
-High priority access support
- Hierarchical PCI configuration mechanism
-Delayed transaction support for AGP-to-DRAM FRAME# semantic reads that can not be serviced immediately
-32-bit upstream address support for inbound AGP and PCI cycles
-32-bit downstream address support for outbound PCI and Fast Write cycles
-AGP Busy/Stop Protocol
-AGP Clamping and Sense Amp Control
Hub Interface to ICH3-M
- 266-MB/s, point-to-point hub interface to ICH3-M
-66-MHz base clock
- Supports the following traffic types to the ICH3-M
-Hub interface-to-AGP memory writes
- Hub interface-to-DRAM
- CPU-to-hub interface
-Messaging
- MSI Interrupt messages
- Power Management state change
- SMI, SCI and SERR error indication
Power Management
-SMRAM space remapping to A0000h (128 KB)
-Supports extended SMRAM space above 256 MB, additional 128K/256K/512K TSEG from Top of Memory, cacheable (cacheability controlled by CPU)
- APM Rev 1.2 compliant power management
-Suspend to System Memory
- ACPI 2.0 Support
-Intel SpeedStep(TM) technology support
- Cache coherency with CPU in sleep mode
- Dynamic Memory Power-down
Package
-Package options
-593-pin FC-BGA (37.5 x 37.5 mm)
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