93L28, 93L28DC, 93L28DMQB Selling Leads, Datasheet
MFG:F Package Cooled:DIP D/C:84+
93L28, 93L28DC, 93L28DMQB
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Info of 93L28
Info of 93L28DC
Info of 93L28DMQB
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About 93L28
PDF/DataSheet Download
Datasheet: 93L28
File Size: 110289 KB
Manufacturer: NSC [National Semiconductor]
Download : Click here to Download
About 93L00
PDF/DataSheet Download
Datasheet: 93L00
File Size: 115723 KB
Manufacturer: NSC [National Semiconductor]
Download : Click here to Download
About 93L28DMQB
PDF/DataSheet Download
Datasheet: 93L28DMQB
File Size: 110289 KB
Manufacturer: NSC [National Semiconductor]
Download : Click here to Download
93L28 General Description
The 93L28 is a high speed serial storage element providing 16 bits of storage in the form of two 8-bit registers. The multifunctional capability of this device is provided by several features: 1) additional gating is provided at the input toboth shift registers so that the input is easily multiplexed between two sources; 2) the clock of each register may be provided separately or together; 3) both the true and complementary outputs are provided from each 8-bit register, and both registers may be master cleared from a common input.
93L28 Maximum Ratings
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage 7V
Input Voltage 5.5V
Operating Free Air Temperature Range
MIL -55 to +125
Storage Temperature Range -65 to +150
Note: The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings. The ``Recommended Operating Conditions'' table will define the conditions for actual device operation.
93L28 Features
2-input multiplexer provided at data input of each register
Gated clock input circuitry
Both true and complementary outputs provided from last bit of each register
Asynchronous master reset common to both registers
Gated clock input circuitry
Both true and complementary outputs provided from last bit of each register
Asynchronous master reset common to both registers
93L28 Connection Diagram
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