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A3P030-VQG100I (PROASIC3), A3P060, A3P060-FGG

Table of contents:
Info of A3P030-VQG100I (PROASIC3)
Info of A3P060
Info of A3P060-FGG

A3P030-VQG100I (PROASIC3), A3P060, A3P060-FGG Selling Leads, Datasheet

MFG:Actel Package Cooled:7500 D/C:08+

A3P030-VQG100I (PROASIC3), A3P060, A3P060-FGG Picture

A3P030-VQG100I (PROASIC3), A3P060, A3P060-FGG Datasheet download

Five Points

Part Number: A3P030-VQG100I (PROASIC3)

MFG: Actel

Package Cooled: 7500

D/C: 08+

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A3P060 General Description

ProASIC3, the third-generation family of Actel Flashb PGAs, offers performance, density, and features beyond those of the ProASIC^PLUS® family. The nonvolatile Flash technology gives ProASIC3 devices the advantage of being a secure, low-power, single-chip solution that is live at power-up. ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.

ProASIC3 devices offer 1 kbit of on-chip, user nonvolatile FlashROM (FROM) memory storage as well as clock conditioning circuitry based on an integrated phaselocked loop (PLL). The A3P030 device has no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 288 user I/Os.

A3P060 Features

Features and Benefits
High-Temperature AEC-Q100Qualified Devices
• Grade 2 105°C TA (115°C TJ)
• Grade 1 125°C TA (135°C TJ)
• PPAP Documentation
Firm-Error Immune
• Only Automotive FPGAs to Offer Firm-Error Immunity
• Can Be Used without Configuration Upset Risk
High Capacity
• 60 k to 1 M System Gates
• Up to 144 kbits of SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Automotive Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
On-Chip User Nonvolatile Memory
• 1 kbit of FlashROM with Synchronous Interface
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532compliant)
• FlashLock® to Secure FPGA Contents (anti-tampering)
Low Power
• 1.5 V Core Voltage
• Support for 1.5-V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages-up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and A3P1000)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the Automotive ProASIC®3
Family
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 350 MHz)
SRAMs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks

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