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AM29F002BT-90PC, AM29F002N-70JC, AM29F002NB

Table of contents:
Info of AM29F002BT-90PC
Info of AM29F002N-70JC
Info of AM29F002NB

AM29F002BT-90PC, AM29F002N-70JC, AM29F002NB Selling Leads, Datasheet

MFG:AMD Package Cooled:N/A D/C:9+

AM29F002BT-90PC, AM29F002N-70JC, AM29F002NB Picture

AM29F002BT-90PC, AM29F002N-70JC, AM29F002NB Datasheet download

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Part Number: AM29F002BT-90PC

MFG: AMD

Package Cooled: N/A

D/C: 9+

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AM29F002NB General Description

The Am29F002B Family consists of 2 Mbit, 5.0 volt-only Flash memory devices organized as 262,144 bytes. The Am29F002B offers the RESET# function, the Am29F002NB does not. The data appears on DQ7DQ0. The device is offered in 32-pin PLCC, 32-pin TSOP, and 32-pin PDIP packages. This device is designed to be programmed in-system with the standard system 5.0 volt V_CC supply. No VPP is required for write or erase operations. The device can also be programmed in standard EPROM programmers.

This device is manufactured using AMD's 0.32 m process technology, and offers all the features and benefits of the Am29F002, which was manufactured using 0.5 m process technology.

The standard device offers access times of 55, 70, 90,and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm-an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm-an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data#Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can beachieved via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

(This feature is not available on the Am29F002NB.) The system can place the device into the standby mode.Power consumption is greatly reduced in this mode. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness.

The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling.The data is programmed using hot electron injection.

AM29F002NB Maximum Ratings

Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . 65 to +150
Ambient Temperature
with Power Applied . . . . . . . . . . . . . 55 to +125
Voltage with Respect to Ground
V_CC (Note 1) . . . . . . . . . . . . . . . .2.0 V to +7.0 V
A9, OE#, and
RESET# (Note 2). . . . . . . . . . . . .2.0 V to +12.5 V
All other pins (Note 1) . . . . . . . . . 0.5 V to +7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, input or I/O pins may overshoot V_SSto 2.0 V for periods of up to 20 ns. See Figure 6.Maximum DC voltage on input or I/O pins is V_CC +0.5 V.During voltage transitions, input or I/O pins may overshoot to V_CC +2.0 V for periods up to 20 ns. See Figure 7.

2. Minimum DC input voltage on pins A9, OE#, and RESET# is 0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to 2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to +13.5 V for periods up to 20 ns. (RESET# is not available on Am29F002NB) 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

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