CD40538CM, CD40538DM, CD4053B Selling Leads, Datasheet
MFG:FOS Package Cooled:SOP16S D/C:2007+
CD40538CM, CD40538DM, CD4053B Datasheet download
Part Number: CD40538CM
MFG: FOS
Package Cooled: SOP16S
D/C: 2007+
CD40538CM, CD40538DM, CD4053B
- Table of contents:
Info of CD40538CM
Info of CD40538DM
Info of CD4053B
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About CD4/74AC563
PDF/DataSheet Download
Datasheet: CD4/74AC563
File Size: 245957 KB
Manufacturer:
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About CD4/74AC563
PDF/DataSheet Download
Datasheet: CD4/74AC563
File Size: 245957 KB
Manufacturer:
Download : Click here to Download
About CD4053B
PDF/DataSheet Download
Datasheet: CD4053B
File Size: 116973 KB
Manufacturer:
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CD4053B Maximum Ratings
Supply Voltage (V+ to V-)
Voltages Referenced to VSS Terminal . . . . . . . . . . -0.5V to 20V
DC Input Voltage Range . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . ±10mA
Voltages Referenced to VSS Terminal . . . . . . . . . . -0.5V to 20V
DC Input Voltage Range . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . ±10mA
CD4053B Features
• Wide Range of Digital and Analog Signal Levels
- Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V
- Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20VP-P
• Low ON Resistance, 125W (Typ) Over 15VP-P Signal Input Range for VDD-VEE = 18V
• High OFF Resistance, Channel Leakage of ±100pA (Typ) at VDD-VEE = 18V
• Logic-Level Conversion for Digital Addressing Signals of 3V to 20V (VDD-VSS = 3V to 20V) to Switch Analog Signals to 20VP-P (VDD-VEE = 20V)
• Matched Switch Characteristics, rON = 5W (Typ) for VDD-VEE = 15V
• Very Low Quiescent Power Dissipation Under All Digital- Control Input and Supply Conditions, 0.2mW (Typ) at VDD-VSS = VDD-VEE = 10V
• Binary Address Decoding on Chip
• 5V, 10V and 15V Parametric Ratings
• 10% Tested for Quiescent Current at 20V
• Maximum Input Current of 1A at 18V Over Full Package Temperature Range, 100nA at 18V and 25oC
• Break-Before-Make Switching Eliminates Channel Overlap
- Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V
- Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20VP-P
• Low ON Resistance, 125W (Typ) Over 15VP-P Signal Input Range for VDD-VEE = 18V
• High OFF Resistance, Channel Leakage of ±100pA (Typ) at VDD-VEE = 18V
• Logic-Level Conversion for Digital Addressing Signals of 3V to 20V (VDD-VSS = 3V to 20V) to Switch Analog Signals to 20VP-P (VDD-VEE = 20V)
• Matched Switch Characteristics, rON = 5W (Typ) for VDD-VEE = 15V
• Very Low Quiescent Power Dissipation Under All Digital- Control Input and Supply Conditions, 0.2mW (Typ) at VDD-VSS = VDD-VEE = 10V
• Binary Address Decoding on Chip
• 5V, 10V and 15V Parametric Ratings
• 10% Tested for Quiescent Current at 20V
• Maximum Input Current of 1A at 18V Over Full Package Temperature Range, 100nA at 18V and 25oC
• Break-Before-Make Switching Eliminates Channel Overlap
CD4053B Typical Application
• Analog and Digital Multiplexing and Demultiplexing
• A/D and D/A Conversion
• Signal Gating
• A/D and D/A Conversion
• Signal Gating
CD4053B Connection Diagram
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