CDP1821SD, CDP1822, CDP18220D Selling Leads, Datasheet
MFG:1300 Package Cooled:CDIP D/C:00+
CDP1821SD, CDP1822, CDP18220D Datasheet download
Part Number: CDP1821SD
MFG: 1300
Package Cooled: CDIP
D/C: 00+
CDP1821SD, CDP1822, CDP18220D
- Table of contents:
Info of CDP1821SD
Info of CDP1822
Info of CDP18220D
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About CDP1020
PDF/DataSheet Download
Datasheet: CDP1020
File Size: 158108 KB
Manufacturer: INTERSIL [Intersil Corporation]
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About CDP1822
PDF/DataSheet Download
Datasheet: CDP1822
File Size: 46193 KB
Manufacturer: INTERSIL [Intersil Corporation]
Download : Click here to Download
About CDP1020
PDF/DataSheet Download
Datasheet: CDP1020
File Size: 158108 KB
Manufacturer: INTERSIL [Intersil Corporation]
Download : Click here to Download
CDP1822 General Description
The CDP1822 and CDP1822C are 256-word by 4-bit static random-access memories designed for use in memory systems where high speed, low operating current, and simplicity in use are desirable. The CDP1822 features high speed and a wide operating voltage range. Both types have separate data inputs and outputs and utilize single power supplies of 4V to 6.5V for the CDP1822C and 4V to 10.5V for the CDP1822.
Two Chip-Select inputs are provided to simplify system expansion. An Output Disable control provides Wire-OR capability and is also useful in common Input/Output systems.
The Output Disable input allows these RAMs to be used in common data Input/Output systems by forcing the output into a high-impedance state during a write operation independent of the Chip-Select input condition. The output assumes a high-impedance state when the Output Disable is at high level or when the chip is deselected by CS1 and/or CS2.
The high noise immunity of the CMOS technology is preserved in this design. For TTL interfacing at 5V operation, excellent system noise margin is preserved by using an external pull-up resistor at each input.
Two Chip-Select inputs are provided to simplify system expansion. An Output Disable control provides Wire-OR capability and is also useful in common Input/Output systems.
The Output Disable input allows these RAMs to be used in common data Input/Output systems by forcing the output into a high-impedance state during a write operation independent of the Chip-Select input condition. The output assumes a high-impedance state when the Output Disable is at high level or when the chip is deselected by CS1 and/or CS2.
The high noise immunity of the CMOS technology is preserved in this design. For TTL interfacing at 5V operation, excellent system noise margin is preserved by using an external pull-up resistor at each input.
CDP1822 Maximum Ratings
DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1822 . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1822C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . .. . . . . . .-0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .±10mA
CDP1822C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . .. . . . . . .-0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .±10mA
CDP1822 Features
• Low Operating Current
- VDD = 5V, Cycle Time 1ms . . . . . . . . . . . . . . . . . . 8mA
• Industry Standard Pinout
• Two Chip-Select Inputs-Simple Memory Expansion
• Memory Retention for Standby Battery Voltage of 2V Minimum
• Output-Disable for Common I/O Systems
• Three-State Data Output for Bus-Oriented Systems
• Separate Data Inputs and Outputs
- VDD = 5V, Cycle Time 1ms . . . . . . . . . . . . . . . . . . 8mA
• Industry Standard Pinout
• Two Chip-Select Inputs-Simple Memory Expansion
• Memory Retention for Standby Battery Voltage of 2V Minimum
• Output-Disable for Common I/O Systems
• Three-State Data Output for Bus-Oriented Systems
• Separate Data Inputs and Outputs
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