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CDP1852D3, CDP1852E, CDP1853

Table of contents:
Info of CDP1852D3
Info of CDP1852E
Info of CDP1853

CDP1852D3, CDP1852E, CDP1853 Selling Leads, Datasheet

MFG:HAR D/C:9820

CDP1852D3, CDP1852E, CDP1853 Datasheet download

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Part Number: CDP1852D3

MFG: HAR

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D/C: 9820

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CDP1853 General Description

The CDP1852/3 and CDP1852C/3 are parallel, 8-bit, modeprogrammable input/output ports. They are compatible and will interface directly with CDP1800-Series microprocessors.

They are also useful as 8-bit address latches when used with the CDP1800 multiplexed address bus and as I/O ports in general-purpose applications.

The mode control is used to program the device as an input port (mode = 0) or as an output port (mode = 1). The SR/SR output can be used as a signal to indicate when data is ready to be transferred. In the input mode, a peripheral device can strobe data into the CDP1852/3, and microprocessor can read that data by device selection. In the output mode, a microprocessor strobes data into the CDP1852/3, and handshaking is established with a peripheral device when the CDP1852/3 is deselected.

In the input mode, data at the data-in terminals (DI0-DI7) is strobed into the port's 8-bit register by a high (1) level on the clock line. The negative high-to-low transition of the clock latches the data in the register and sets the service request output low (SR/SR = 0). When CS1/CS1 and CS2 are high (CS1/CS1 and CS2 = 1), the three-state output drivers are enabled and data in the 8-bit register appear at the data-out terminals (DO0-DO7). When either CS1/CS1 or CS2 goes low (CS1/CS1 or CS2 = 0), the data-out terminals are tristated and the service request output returns high (SR/SR =1).

In the output mode, the output drivers are enabled at all times. Data at the data-in terminals (DI0-DI7) is strobed into the 8-bit register when CS1/CS1 is low (CS1/CS1 = 0) and CS2 and the clock are high (1), and are present at the dataout terminals (DO0-DO7). The negative high-to-low transition of the clock latches the data in the register. The SR/SR output goes high (SR/SR = 1) when the device is deselected (CS1/CS1 = 1 or CS2 = 0) and returns low (SR/SR = 0) on the following trailing edge of the clock.

A CLEAR control is provided for resetting the port's register (DO0-DO7 = 0) and service request flip-flop (input mode: SR/SR = 1 and output mode: SR/SR = 0).

The CDP1852/3 is functionally identical to the CDP1852C/3.

The CDP1852/3 has a recommended operating voltage range of 4V to 10.5V, and the CDP1852C/3 has a recommended operating voltage range of 4V to 6.5V.

The CDP1852/3 and CDP1852C/3 are supplied in 24-lead, dual-in-line side-brazed ceramic packages (D suffix).

CDP1853 Maximum Ratings

DC Supply Voltage Range, (V_DD):
(All Voltages Referenced to V_SS Terminal)
CDP1852/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1852C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . -0.5V to V_DD +0.5V
DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . ±10mA

CDP1853 Features

• Static Silicon-Gate CMOS Circuitry
• Parallel 8-Bit Data Register and Buffer
• Handshaking Via Service Request Flip-Flop
• Low Quiescent and Operating Power
• Interfaces Directly with CDP1800-Series Microprocessors
• Single Voltage Supply
• Full Military Temperature Range (-55 to +125)

CDP1853 Connection Diagram

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