CDP1877, CDP1877ACE, CDP1877CE Selling Leads, Datasheet
MFG:HAR Package Cooled:DIP D/C:02+
CDP1877, CDP1877ACE, CDP1877CE Datasheet download
Part Number: CDP1877
MFG: HAR
Package Cooled: DIP
D/C: 02+
CDP1877, CDP1877ACE, CDP1877CE
- Table of contents:
Info of CDP1877
Info of CDP1877ACE
Info of CDP1877CE
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About CDP1877
PDF/DataSheet Download
Datasheet: CDP1877
File Size: 46921 KB
Manufacturer: INTERSIL [Intersil Corporation]
Download : Click here to Download
About CDP1020
PDF/DataSheet Download
Datasheet: CDP1020
File Size: 158108 KB
Manufacturer: INTERSIL [Intersil Corporation]
Download : Click here to Download
About CDP1877CE
PDF/DataSheet Download
Datasheet: CDP1877CE
File Size: 46921 KB
Manufacturer: INTERSIL [Intersil Corporation]
Download : Click here to Download
CDP1877 General Description
The CDP1877 and CDP1877C are programmable 8-level interrupt controllers designed for use in CDP1800 series microprocessor systems. They provide added versatility by extending the number of permissible interrupts from 1 to N in increments of 8.
When a high to low transition occurs on any of the PIC interrupt lines (IR0 to IR7), it will be latched and, unless the request is masked, it will cause the INTERRUPT line on the PIC and consequently the INTERRUPT input on the CPU to go low.
The CPU accesses the PIC by having interrupt vector register R(1) loaded with the memory address of the PIC. After the interrupt S3 cycle, this register value will appear at the CPU address bus, causing the CPU to fetch an instruction from the PIC. This fetch cycle clears the interrupt request latch bit to accept a new high-to-low transition, and also causes the PIC to issue a long branch instruction (CO) followed by the preprogrammed vector address written into the PIC's address registers, causing the CPU to branch to the address corresponding to the highest priority active interrupt request.
If no other unmasked interrupts are pending, the INTERRUPT output of the PIC will return high. When an interrupt is requested on a masked interrupt line, it will be latched but it will not cause the PIC INTERRUPT output to go low. All pending interrupts, masked and unmasked, will be indicated by a "1" in the corresponding bit of the status register. Reading of the status register will clear all pending interrupt request latches.
Several PICs can be cascaded together by connecting the INTERRUPT output of one chip to the CASCADE input of another. Each cascaded PIC provides 8 additional interrupt levels to the system. The number of units cascadable depends on the amount of memory space and the extent of the address decoding in the system.
Interrupts are prioritized in descending order; IR7 has the highest and IR0 has the lowest priority.
The CDP1877 and CDP1877C are functionally identical. They differ in that the CDP1877 has a recommended operating voltage range of 4V to 10.5V, and the CDP1877C has a recommended operating voltage range of 4V to 6.5V.
CDP1877 Maximum Ratings
DC Supply-Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal)
CDP1877. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1877C . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . .±10mA
(All Voltages Referenced to VSS Terminal)
CDP1877. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1877C . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . .±10mA
CDP1877 Features
• Compatible with CDP1800 Series
• Programmable Long Branch Vector Address and Vector Interval
• 8 Levels of Interrupt Per Chip
• Easily Expandable
• Latched Interrupt Requests
• Hard Wired Interrupt Priorities
• Memory Mapped
• Multiple Chip Select Inputs to Minimize Address Space Requirements
• Programmable Long Branch Vector Address and Vector Interval
• 8 Levels of Interrupt Per Chip
• Easily Expandable
• Latched Interrupt Requests
• Hard Wired Interrupt Priorities
• Memory Mapped
• Multiple Chip Select Inputs to Minimize Address Space Requirements
CDP1877 Connection Diagram
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