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The CDP1883 is a CMOS 7-bit memory latch and decoder circuit intended for use in CDP1800-series microprocessor systems. It can serve as a direct interface between the multiplexed address bus of this system and up to four 8K x 8-bit memories to implement a 32K-byte memory system. With four 4K x 8-bit memories, a 16K-byte system can be decoded. The device is also compatible with non-multiplexed address bus microprocessors. By connecting the clock input to VDD, the latches are in the data-following mode and the decoded outputs can be used in general-purpose memory-system applications. The CDP1833 is compatible with CDP1800-series microprocessors operating at maximum clock frequency. The CDP1883 and CDP1883C are functionally identical. They differ in that the CDP1883 has a recommended operating voltage range of 4V to 10.5V and the C version has a recommended operating voltage range of 4V to 6.5V. The CDP1883 and CDP1883C are supplied in 20 lead dualin- line plastic packages (E Suffix).
• Performs Memory Address Latch and Decoder Functions Multiplexed or Non-Multiplexed • Interfaces Directly with the CDP1800-Series Microprocessors • Allows Decoding for Systems Up to 32K Bytes