CDP68HC68P1, CDP68HC68P1E, CDP68HC68P1M Selling Leads, Datasheet
MFG:INTERSIL Package Cooled:SOP16 D/C:00+
CDP68HC68P1, CDP68HC68P1E, CDP68HC68P1M Datasheet download
Part Number: CDP68HC68P1
MFG: INTERSIL
Package Cooled: SOP16
D/C: 00+
CDP68HC68P1, CDP68HC68P1E, CDP68HC68P1M
- Table of contents:
Info of CDP68HC68P1
Info of CDP68HC68P1E
Info of CDP68HC68P1M
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About CDP68HC68P1
PDF/DataSheet Download
Datasheet: CDP68HC68P1
File Size: 259290 KB
Manufacturer: INTERSIL [Intersil Corporation]
Download : Click here to Download
About CDP68HC68P1E
PDF/DataSheet Download
Datasheet: CDP68HC68P1E
File Size: 259290 KB
Manufacturer: INTERSIL [Intersil Corporation]
Download : Click here to Download
About CDP68HC68P1M
PDF/DataSheet Download
Datasheet: CDP68HC68P1M
File Size: 259290 KB
Manufacturer: INTERSIL [Intersil Corporation]
Download : Click here to Download
CDP68HC68P1 Parameters
- Fully Static Operation
- Operating Voltage Range 3-6V
- Compatible with Intersil/Motorola SPI Bus
- 2 External Address Pins Tied to VDD or VSS to Allow Up to 4 Devices to Share the Same Chip Enable
- Versatile Bit-Set and Bit-Clear Capability
- Accepts Either SCK Clock Polarity - SCK Voltage Level is Latched When Chip Enable Goes Active
- All Inputs are Schmitt-Trigger
- 8-Bit I/O Port - Each Bit can be Individually Programmed as an Input or Output Via an 8-Bit Data Direction Register
- Programmable On Board Comparator
- Simultaneous Transfer of Compare Information to CPU During Read or Write - Separate Access Not Required
CDP68HC68P1 General Description
Port, Input/Output, Serial, 8-Bit, CMOS
CDP68HC68P1 Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . .. . . -0.5V to +7V
(Voltage Referenced to VSS Terminal)
Input Voltage Range, All Inputs . . . . . . . . . ... . -0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . .. . . . . . . ±10mA
Power Dissipation Per Package (PD)
TA = -40oC to 60oC (Package Type E) . . . . . . . . . . . . . . .500mW
TA = 60oC to 85oC (Package Type E)
Derate Linearly at . . . . . . . . . . . . . . . . . . . 12mW/oC to 200mW
TA = -40oC to 60oC (Package Type M) (Note 1) . . oC. . .300mW
TA = 60oC to 85oC (Package Type M) (Note 1)
Derate Linearly at . . . . . . . . . . . . . . . . . . . . 5mW/oC to 175mW
(Voltage Referenced to VSS Terminal)
Input Voltage Range, All Inputs . . . . . . . . . ... . -0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . .. . . . . . . ±10mA
Power Dissipation Per Package (PD)
TA = -40oC to 60oC (Package Type E) . . . . . . . . . . . . . . .500mW
TA = 60oC to 85oC (Package Type E)
Derate Linearly at . . . . . . . . . . . . . . . . . . . 12mW/oC to 200mW
TA = -40oC to 60oC (Package Type M) (Note 1) . . oC. . .300mW
TA = 60oC to 85oC (Package Type M) (Note 1)
Derate Linearly at . . . . . . . . . . . . . . . . . . . . 5mW/oC to 175mW
CDP68HC68P1 Features
- Fully Static Operation
- Operating Voltage Range 3-6V
- Compatible with Intersil/Motorola SPI Bus
- 2 External Address Pins Tied to VDD or VSS to Allow Up to 4 Devices to Share the Same Chip Enable
- Versatile Bit-Set and Bit-Clear Capability
- Accepts Either SCK Clock Polarity - SCK Voltage Level is Latched When Chip Enable Goes Active
- All Inputs are Schmitt-Trigger
- 8-Bit I/O Port - Each Bit can be Individually Programmed as an Input or Output Via an 8-Bit Data Direction Register
- Programmable On Board Comparator
- Simultaneous Transfer of Compare Information to CPU During Read or Write - Separate Access Not Required
CDP68HC68P1 Typical Application
CDP68HC68P1 Datasheet
CDP68HC68P1 Connection Diagram
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