CY3130, CY3130R62, CY3138 Selling Leads, Datasheet
MFG:CYPRESS Package Cooled:N/A D/C:09+
CY3130, CY3130R62, CY3138 Datasheet download
Part Number: CY3130
MFG: CYPRESS
Package Cooled: N/A
D/C: 09+
CY3130, CY3130R62, CY3138
- Table of contents:
Info of CY3130
Info of CY3130R62
Info of CY3138
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About CY3130
PDF/DataSheet Download
Datasheet: CY3130
File Size: 140729 KB
Manufacturer: Cypress
Download : Click here to Download
About CY3130R62
PDF/DataSheet Download
Datasheet: CY3130R62
File Size: 397714 KB
Manufacturer: CYPRESS
Download : Click here to Download
About CY3138
PDF/DataSheet Download
Datasheet: CY3138
File Size: 397714 KB
Manufacturer: CYPRESS
Download : Click here to Download
CY3130 General Description
Warp3 is an integration of Cypress's advanced VHDL and Verilog synthesis and fitting technology with Viewlogic's sophisticated EDA design environment. Warp3 includes Cypress's VHDL and Verilog compiler and Workview Office software for Windows 95™, Windows 98™, and Windows NT™.
CY3130 Features
• Sophisticated CPLD design and verification system based on VHDL and Verilog
• Warp3® is based on the Workview Office® (PC) design environment
-Advanced graphical user interface for Windows®
-Schematic capture (ViewDraw®)
-VHDL source-level simulator (SpeedWave®)
-Interactive timing simulator (ViewSim®)
-Waveform stimulus and viewing (ViewTrace®)
-Textual design entry using VHDL and Verilog
-Mixed-mode (schematics and text) design entry support for VHDL
• The core of Warp3 consists of an IEEE1076 and 1164 standard VHDL and an IEEE 1364 Verilog compiler
-Open, powerful design languages
-Facilitate design portability across devices and/or CAD platforms
-Facilitate the use of industry-standard simulation and synthesis tools for board and system-level design
• Additional option for timing simulation and an FSM editor from Aldec
-Active-HDL™ Sim Release 3.3 graphical waveform simulator
-Active-HDL FSM graphical Finite State Machine editor
• Support for ALL Cypress PLDs and CPLDs including:
-Ultra37000™ CPLDs (now with FBGA support)
-FLASH370i™ CPLDs
-MAX340™ CPLDs
-Industry-standard PLDs (16v8, 20v8, 22v10)
• Warp3® is based on the Workview Office® (PC) design environment
-Advanced graphical user interface for Windows®
-Schematic capture (ViewDraw®)
-VHDL source-level simulator (SpeedWave®)
-Interactive timing simulator (ViewSim®)
-Waveform stimulus and viewing (ViewTrace®)
-Textual design entry using VHDL and Verilog
-Mixed-mode (schematics and text) design entry support for VHDL
• The core of Warp3 consists of an IEEE1076 and 1164 standard VHDL and an IEEE 1364 Verilog compiler
-Open, powerful design languages
-Facilitate design portability across devices and/or CAD platforms
-Facilitate the use of industry-standard simulation and synthesis tools for board and system-level design
• Additional option for timing simulation and an FSM editor from Aldec
-Active-HDL™ Sim Release 3.3 graphical waveform simulator
-Active-HDL FSM graphical Finite State Machine editor
• Support for ALL Cypress PLDs and CPLDs including:
-Ultra37000™ CPLDs (now with FBGA support)
-FLASH370i™ CPLDs
-MAX340™ CPLDs
-Industry-standard PLDs (16v8, 20v8, 22v10)
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