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DP83846AVHGC4, DP83847, DP83847A5

Table of contents:
Info of DP83846AVHGC4
Info of DP83847
Info of DP83847A5

DP83846AVHGC4, DP83847, DP83847A5 Selling Leads, Datasheet

MFG:TQFP-80P Package Cooled:NSC D/C:00+

DP83846AVHGC4, DP83847, DP83847A5 Picture

DP83846AVHGC4, DP83847, DP83847A5 Datasheet download

Five Points

Part Number: DP83846AVHGC4

MFG: TQFP-80P

Package Cooled: NSC

D/C: 00+

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DP83846AVHGC4 Parameters

DP83847 Features

Low-power 3.3V, 0.18um CMOS technology
Power consumption < 351mW (typical)
5V tolerant I/Os
5V/3.3V MAC interface
IEEE 802.3 ENDEC, 10BASE-T transceivers and filters
IEEE 802.3u PCS, 100BASE-TX transceivers and filters
IEEE 802.3 compliant Auto-Negotiation
Output edge rate control eliminates external filtering for Transmit outputs
BaseLine Wander compensation
IEEE 802.3u MII (16 pins/port)
LED support (Link, Rx, Tx, Duplex, Speed, Collision)
Single register access for complete PHY status
10/100 Mb/s packet loopback BIST (Built in Self Test)
56-pin LLP package (9w) x (9l) x (.75h) mm

DP83846AVHGC4 General Description

DsPHYTER II - Single 10/100 Ethernet Transceiver

DP83846AVHGC4 Features

Low-power 3.3V, 0.18um CMOS technology
Power consumption < 351mW (typical)
5V tolerant I/Os
5V/3.3V MAC interface
IEEE 802.3 ENDEC, 10BASE-T transceivers and filters
IEEE 802.3u PCS, 100BASE-TX transceivers and filters
IEEE 802.3 compliant Auto-Negotiation
Output edge rate control eliminates external filtering for Transmit outputs
BaseLine Wander compensation
IEEE 802.3u MII (16 pins/port)
LED support (Link, Rx, Tx, Duplex, Speed, Collision)
Single register access for complete PHY status
10/100 Mb/s packet loopback BIST (Built in Self Test)
56-pin LLP package (9w) x (9l) x (.75h) mm

DP83846AVHGC4 Typical Application

DP83847 Datasheet

DP83847 Parameters

DP83847 Features

Low-power 3.3V, 0.18um CMOS technology
Power consumption < 351mW (typical)
5V tolerant I/Os
5V/3.3V MAC interface
IEEE 802.3 ENDEC, 10BASE-T transceivers and filters
IEEE 802.3u PCS, 100BASE-TX transceivers and filters
IEEE 802.3 compliant Auto-Negotiation
Output edge rate control eliminates external filtering for Transmit outputs
BaseLine Wander compensation
IEEE 802.3u MII (16 pins/port)
LED support (Link, Rx, Tx, Duplex, Speed, Collision)
Single register access for complete PHY status
10/100 Mb/s packet loopback BIST (Built in Self Test)
56-pin LLP package (9w) x (9l) x (.75h) mm

DP83847 General Description

DsPHYTER II - Single 10/100 Ethernet Transceiver

DP83847 Features

Low-power 3.3V, 0.18um CMOS technology
Power consumption < 351mW (typical)
5V tolerant I/Os
5V/3.3V MAC interface
IEEE 802.3 ENDEC, 10BASE-T transceivers and filters
IEEE 802.3u PCS, 100BASE-TX transceivers and filters
IEEE 802.3 compliant Auto-Negotiation
Output edge rate control eliminates external filtering for Transmit outputs
BaseLine Wander compensation
IEEE 802.3u MII (16 pins/port)
LED support (Link, Rx, Tx, Duplex, Speed, Collision)
Single register access for complete PHY status
10/100 Mb/s packet loopback BIST (Built in Self Test)
56-pin LLP package (9w) x (9l) x (.75h) mm

DP83847 Typical Application

DP83847 Datasheet

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