EX256, EX256-FTQG100717, EX256-TQ100465 Selling Leads, Datasheet
MFG:ACTEL Package Cooled:BGA D/C:08+09+
EX256, EX256-FTQG100717, EX256-TQ100465 Datasheet download
Part Number: EX256
MFG: ACTEL
Package Cooled: BGA
D/C: 08+09+
EX256, EX256-FTQG100717, EX256-TQ100465
- Table of contents:
Info of EX256
Info of EX256-FTQG100717
Info of EX256-TQ100465
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About EX256-FCS49PP
PDF/DataSheet Download
Datasheet: EX256-FCS49PP
File Size: 314585 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
About EX256-FCS49PP
PDF/DataSheet Download
Datasheet: EX256-FCS49PP
File Size: 314585 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
About EX256-FCS49PP
PDF/DataSheet Download
Datasheet: EX256-FCS49PP
File Size: 314585 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
EX256 General Description
The eX family of FPGAs is a low-cost solution for low-power, high-performance designs. The inherent low power attributes of the antifuse technology, coupled with an additional low static power mode, make these devices ideal for power-sensitive applications. Fabricated with an advanced 0.22 CMOS antifuse technology, these devices achieve high performance with no power penalty.
EX256 Maximum Ratings
| Symbol |
Parameter | Limits | Units |
|---|---|---|---|
| VCCI | DC Supply Voltage | 0.3 to +6.0 | V |
| VCCA | DC Supply Voltage | 0.3 to +3.0 | V |
| VI | Input Voltage | 0.5 to +5.5 | V |
| VO | Output Voltage | 0.5 to +VCCI + 0.5 | V |
| TSTG | Storage Temperature | 65 to +150 | °C |
EX256 Features
• LP/Sleep Mode for Additional Power Savings
• Advanced Small-footprint Packages
• Hot-Swap Compliant I/Os
• Single-Chip Solution
• Nonvolatile
• Live on power up
• Power-Up/Down Friendly (No Sequencing Required for Supply Voltages)
• Configurable Weak-Resistor Pull-Up or Pull-Down for Tristated Outputs during Power Up
• Individual Output Slew Rate Control
• 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength
• Software Design Support with Actel Designer Series and Libero Tools
• Up to 100% Resource Utilization with 100% Pin Locking
• Deterministic Timing
• Unique In-System Diagnostic and Verification Capability with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse Engineering and Design Theft
EX256 Connection Diagram
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