FSTUD162211MTD, FSTUD162450, FSTUD162450GX Selling Leads, Datasheet
MFG:FSX Package Cooled:TSSOP D/C:04+
FSTUD162211MTD, FSTUD162450, FSTUD162450GX Datasheet download

Part Number: FSTUD162211MTD
MFG: FSX
Package Cooled: TSSOP
D/C: 04+
MFG:FSX Package Cooled:TSSOP D/C:04+
FSTUD162211MTD, FSTUD162450, FSTUD162450GX Datasheet download

MFG: FSX
Package Cooled: TSSOP
D/C: 04+
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PDF/DataSheet Download
Datasheet: FST10020
File Size: 135828 KB
Manufacturer: MCC [Micro Commercial Components]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: FSTUD162450
File Size: 575305 KB
Manufacturer: FAIRCHILD [Fairchild Semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: FSTUD162450GX
File Size: 575305 KB
Manufacturer: FAIRCHILD [Fairchild Semiconductor]
Download : Click here to Download
The Fairchild Universal Bus Switch FSTUD162450 provides 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit of high-speed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise.
The FSTUD162450 is designed to allow "customer" configuration control of the enable connections. The device can be organized as either a five 4-bit, four 5-bit, two 10-bit or one 20-bit bus switch. Also available are 8-bit and 16-bit enabled configurations (see Functional Description). The device's bit configuration is controlled through select pin logic. (see Truth Table). When OEx is LOW, Port Ax is connected to Port Bx. When OEx is HIGH, the switch is OPEN.
The A and B Ports are protected against undershoot to support an extended range to 2.0V below ground.
Fairchild's integrated Undershoot Hardened Circuit (UHC) senses undershoot at the I/O and responds by preventing voltage differentials from developing and turning the switch on.
Another innovative device feature is the addition of a level shifting select pin, "S2". When S2 is LOW, the device behaves as a standard N-MOS switch. When S2 is HIGH, a diode to VCC is integrated into the circuit allowing for level shifting between 5V inputs and 3.3V outputs.
Supply Voltage (VCC) ..................................−0.5V to +7.0V
DC Switch Voltage (VS) (Note 3) .................−2.0V to +7.0V
DC Input Control Pin Voltage
(VIN) (Note 4) ..............................................−0.5V to +7.0V
DC Input Diode Current (lIK) VIN < 0V .....................−50 mA
DC Output (IOUT) Current .......................................128 mA
DC VCC/GND Current (ICC/IGND) ........................+/− 100 mA
Storage Temperature Range (TSTG) ..........−65 to +150
Power Supply Operating (VCC) .........................4.0V to 5.5V
Input Voltage (VIN) ..............................................0V to 5.5V
Output Voltage (VOUT) .........................................0V to 5.5V
Free Air Operating Temperature (TA) ............-40 to +85
Note 2: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Note 3: VS is the voltage observed/applied at either the A or B Ports across the switch.
Note 4: The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed.
Note 5: Unused control inputs must be held HIGH or LOW. They may not float.
` Undershoot protected to −2V (A and B Ports)
` Voltage level shifting
` 25 switch connection between two ports
` Minimal propagation delay through the switch
` Low lCC
` Zero bounce in flow-through mode
` Control inputs compatible with TTL level
` See Applications Notes AN-5008 and AN-5021 for UHC details
` Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)
Select pins S0, S1, S2 are intended to be used as static user configurable control pins. The AC performance of these pins has not been characterized or tested. Switching of these select pins during system operation may temporarily disrupt output logic states and/or enable pin controls.

