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HDMP-0482, HDMP0552, HDMP-0552

Table of contents:
Info of HDMP-0482
Info of HDMP0552
Info of HDMP-0552

HDMP-0482, HDMP0552, HDMP-0552 Selling Leads, Datasheet

MFG:AVAGO/Agilent Package Cooled:Original Package D/C:08+/09+

HDMP-0482, HDMP0552, HDMP-0552 Datasheet download

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Part Number: HDMP-0482

MFG: AVAGO/Agilent

Package Cooled: Original Package

D/C: 08+/09+

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HDMP-0482 General Description

The HDMP-0482 is an Octal Cell Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) and data valid detection capability included. This device minimizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. By using Port Bypass Circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system.

A Port Bypass Circuit (PBC) consists of multiple 2:1 multiplexers daisy chained along with a CDR. Each port has two modes of operation: "disk in loop" and "disk bypassed". When the "diskin loop" mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0482's TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC's (e.g. an HDMP-1636A) Rx± differential input pins. Data from the Disk Drive Transceiver IC's Tx± differential outputs goes tothe HDMP-0482's FM_NODE[n]± differential input pins. When the "disk bypassed" mode is selected, the disk drive is either absent or non-functional and the loop bypasses the hard disk.

The "disk bypassed" mode is enabled by pulling the BYPASS[n]- pin low. Leave BYPASS[n]- floating to enable the "disk in loop" mode. HDMP-0482's may be cascaded with other members of the HDMP-04XX/HDMP-05XX family through the FM_NODE and TO_NODE pins to accommodate any number of hard disks. The unused cells in this PBC may be bypassed by using pulldown resistors on the BYPASS[n]- pins for these cells.

An HDMP-0482 may also be used as eight 1:1 buffers, one with a CDR and seven without. For example, an HDMP-0482 may be placed in front of a CMOS ASIC to clean the jitter of the outgoing signal (CDR path) and to better read the incoming signal (non- CDR path). In addition, the HDMP-0482 may be configured as four 2:1 multiplexers or as four 1:2 buffers.

HDMP-0482 Maximum Ratings

T_a=25, except as specified. Operation in excess of any of these conditions may result in permanent damage to his device. Ta refers to the ambient temperature for the board upon which the parametric measurements were ken.

Symbol	Parameters	Min.	Max.	Units
V_CC	Supply Voltage	-0.7	4.0	V
V_{IN, LVTTL}	LVTTL Input Voltage	-0.7	4.0	V
V_{IN, HS_IN}	HS_IN Input Voltage	1.3	V_CC	V
I_{O, LVTTL}	LVTTL Output Voltage		±13	mA
T_stg	Storage Temperature	-65	+150
T_j	Junction Temperature	0	+125

HDMP-0482 Features

• Supports 1.0625 GBd fibre channel
operation
• Supports 1.25 GBd Gigabit Ethernet (GE) operation
• Octal cell PBC/CDR in one package
• CDR location determined by choice of cable input/output
• Amplitude valid detection on FM_NODE[7] input
• Data valid detection on FM_NODE[0] input
Run length violation detection
Comma detection
Configurable for both singleframe and multi-frame detection
• Equalizers on all inputs
• High speed LVPECL I/O
• Buffered Line Logic (BLL) outputs (no external bias resistors required)
• 1.09 W typical power at Vcc=3.3V
• 64 Pin, 14 mm, low cost plastic QFP package

HDMP-0482 Typical Application

• RAID, JBOD, BTS cabinets
• Four 2:1 muxes
• Four 1:2 buffers
• 1 = > N gigabit serial buffer
• N = > 1 gigabit serial mux

HDMP-0482 Connection Diagram

HDMP-0552 General Description

The HDMP-0552 is a Quad Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) and data valid detection capability included. See Figure 1 for block diagram. This device minimizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. By using Port Bypass Circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system.

A PBC consists of multiple 2:1 multiplexers daisy chained along with a CDR. Each port has two modes of operation: "disk in loop" and "disk bypassed." When the "disk in loop" mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0552's TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC (for example, an HDMP-263x) Rx± differential input pins. Data from the Disk Drive Transceiver IC Tx± differential output pins goes to HDMP-0552's FM_NODE[n]± differential input pins. Figure 2 and Figure 3 show connection diagrams for disk drive array applications.

When the "disk bypassed" mode is selected, the disk drive is either absent or nonfunctional, and the loop bypasses the hard disk. Multiple HDMP-0552's may be cascaded or connected to other members of the HDMP-04xx family through the FM_LOOP and TO_LOOP pins to create loops for arrays of disk drives greater than 4. See Table 3 to identify which of the 5 cells (0:4) provides FM_LOOP, TO_LOOP pins (cell connected to cable).

HDMP-0552 Maximum Ratings

Symbol	Parameter	Units	Minimum	Maximum
V_CC	Supply Voltage	V	-0.7	4.0
V_IN, LV_TTL	LVTTL Input Voltage	V	-0.7	5.0
V_IN,H_{S_IN}	HS_IN Input Voltage	V	2.0	V_CC
I_O,L_VTTL	LVTTL Output Current	mA		+13
T_stg	Storage Temperature	°C	-65	+150
T_j	Junction Temperature	°C	0	+125

HDMP-0552 Features

• Supports 1.0625/2.125 GBd Fibre Channel operation
• Quad PBC/CDR in one package
• CDR location determined by choice of cable input/output
• Amplitude valid detection on FM_NODE[0] input
• Data valid detection on FM_NODE[0] input
Run length violation detection
Comma detection
Configurable for both singleframe and multi-frame detection
• Speed select pin for 1 or 2 GBd operation
• Single REFCLK for 1 or 2 GBd operation
• CDR selectable via external pin
• Enable/disable equalizers on all inputs
• Enable/disable selected highspeed output drivers
• High speed LVPECL I/O
• Buffered line logic (BLL) outputs (no external bias resistors required)
• 1.1 W typical power at VCC = 3.3 V
• Advanced 0.35 µ BiCMOS technology
• 64 Pin, 10 mm, low cost plastic QFP package

HDMP-0552 Typical Application

• RAID, JBOD, BTS cabinets
• 1=> 1-4 serial buffer with or without CDR

HDMP-0552 Connection Diagram

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