MFG:HYNIX Package Cooled:TSSOP-66 D/C:2005+
HY5DU281622AT-L, HY5DU281622EFP, HY5DU281622ET Datasheet download
MFG: HYNIX
Package Cooled: TSSOP-66
D/C: 2005+
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PDF/DataSheet Download
Datasheet: HY50P
File Size: 121146 KB
Manufacturer: LEM [LEM]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: HY50P
File Size: 121146 KB
Manufacturer: LEM [LEM]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: HY5DU281622ET
File Size: 388172 KB
Manufacturer: HYNIX [Hynix Semiconductor]
Download : Click here to Download
The Hynix HY5DU281622ET is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which require high densities and high bandwidth.
The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter- nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.
| Parameter | Symbol | Rating | Unit |
| Ambient Temperature | TA | 0 ~ 70 | °C |
| Storage Temperature | TSTG | -55 ~ 125 | °C |
| Voltage on Any Pin relative to VSS | VIN, VOUT | -1.0 ~ 4.6 | V |
| Voltage on VDD relative to VSS | VDD | -1.0 ~ 4.6 | V |
| Short Circuit Output Current | IOS | 50 | mA |
| Power Dissipation | PD | 1 | W |
| Soldering Temperature·Time | TSOLDER | 260·10 | °C ·Sec |
2.8V +/- 0.1V VDD and VDDQ power supply
supports 400/375/350/333/300MHz
2.5V +/- 5% VDD and VDDQ power supply
supports 275/250/200/166MHz
All inputs and outputs are compatible with SSTL_2
interface
JEDEC Standard 400 mil x 875 mil 66 Pin TSOP II,
with 0.65mm pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (UDQS,LDQS)
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Write mask byte controls by DM (UDM,LDM)
Programmable /CAS Latency 5, 4 and 3 are sup-
ported
Programmable Burst Length 2, 4 and 8 with both
sequential and interleave mode
Internal 4 bank operation with single pulsed /RAS
tRAS Lock-Out function are supported
Auto refresh and self refresh are supported
4096 refresh cycles / 32ms
Full strength, Half strength and Weak Impedance
driver options controlled by EMRS
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