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IC42S160100-7TG, IC42S16100, IC42S16100-5T

Table of contents:
Info of IC42S160100-7TG
Info of IC42S16100
Info of IC42S16100-5T

IC42S160100-7TG, IC42S16100, IC42S16100-5T Selling Leads, Datasheet

MFG:ISSI\ICS Package Cooled:7912+ D/C:5000

IC42S160100-7TG, IC42S16100, IC42S16100-5T Picture

IC42S160100-7TG, IC42S16100, IC42S16100-5T Datasheet download

Five Points

Part Number: IC42S160100-7TG

MFG: ISSI\ICS

Package Cooled: 7912+

D/C: 5000

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IC42S16100 General Description

ICSI's 16Mb Synchronous DRAM IC42S16100 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.

IC42S16100 Maximum Ratings

Symbol	Parameters	Rating	Unit
V_{CC MAX}	Maximum Supply Voltage	1.0 to +4.6	V
V_{CCQ MAX}	Maximum Supply Voltage for Output Buffer	1.0 to +4.6	V
V_IN	Input Voltage	1.0 to +4.6	V
V_OUT	Output Voltage	1.0 to +4.6	V
P_{D MAX}	Allowable Power Dissipation	1	W
I_CS	Output Shorted Current	50	mA
T_OPR	Operating Temperature	0 to +70
T_STG	Storage Temperature	55 to +150

IC42S16100 Features

• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11 (bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
(1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto refresh, self refresh
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Byte controlled by LDQM and UDQM
• Package 400mil 50-pin TSOP-2
• Pb(lead)-free package is available

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