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The IDT72V3682/72V3692/72V36102 are designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are monolithic, high-speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memories which support clock frequencies up to 100MHz and have read access times as fast as 6.5ns. Two independent 16,384/32,768/65,536 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored.
These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.
These devices have two modes of operation: In the IDT Standard mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the First Word Fall Through mode (FWFT), the first long-word (36-bit wide) written to an empty FIFO appears automatically on the outputs, no read operation required (Nevertheless, accessing subsequent words does necessitate a formal read request). The state of the FWFT pin during FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB). The EF and FF functions are selected in the IDT Standard mode. EF indicates
IDT72V3692 Maximum Ratings
Symbol
Rating
Commercial
Unit
VCC
Supply Voltage Range
0.5 to +4.6
V
VI(2)
Input Voltage Range
0.5 to VCC+0.5
V
VO(2)
Output Voltage Range
0.5 to VCC+0.5
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
±20
mA
IOK
Output Clamp Current (VO = < 0 or VO > VCC)
±50
mA
IOUT
Continuous Output Current (VO = 0 to VCC)
±50
mA
ICC
Continuous Current Through VCC or GND
±400
mA
TSTG
Storage Temperature Range
65 to 150
°C
NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
IDT72V3692 Features
` Memory storage capacity: IDT72V3682 16,384 x 36 x 2 IDT72V3692 32,768 x 36 x 2 IDT72V36102 65,536 x 36 x 2 ` Supports clock frequencies up to 100MHz ` Fast access times of 6.5ns ` Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) ` Two independent clocked FIFOs buffering data in opposite directions ` Mailbox bypass register for each FIFO ` Programmable Almost-Full and Almost-Empty flags ` Microprocessor Interface Control Logic ` FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA ` FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB ` Select IDT Standard timing (using EFA, EFB, FFA and FFB flags functions) or First Word Fall Through timing (using ORA, ORB, IRA and IRB flag functions) ` Available in space-saving 120-pin Thin Quad Flatpack (TQFP) ` Pin compatible to the lower density parts, IDT72V3622/72V3632/ 72V3642/72V3652/72V3662/72V3672 ` Industrial temperature range (40°C to +85°C) is available