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IDT74ALVC16841, IDT74ALVC2245AQ, IDT74ALVC244

Table of contents:
Info of IDT74ALVC16841
Info of IDT74ALVC2245AQ
Info of IDT74ALVC244

IDT74ALVC16841, IDT74ALVC2245AQ, IDT74ALVC244 Selling Leads, Datasheet

MFG:IDT Package Cooled:N/A D/C:09+

IDT74ALVC16841, IDT74ALVC2245AQ, IDT74ALVC244 Picture

IDT74ALVC16841, IDT74ALVC2245AQ, IDT74ALVC244 Datasheet download

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Part Number: IDT74ALVC16841

MFG: IDT

Package Cooled: N/A

D/C: 09+

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IDT74ALVC16841 General Description

This 20-bit bus-interface D-type latch is built using advanced dual metal CMOS technology. The ALVC16841 features 3-state outputs designed specifically for driving highly capacitive relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, unidirectional bus drivers, and working registers. The ALVC16841 can be used as two 10-bit latches or one 20-bit latch.

The 20 latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The ALVC16841 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

IDT74ALVC16841 Maximum Ratings

Symbol	Rating	Max	Unit
V_TERM (V_DD)	VDD Terminal Voltage with Respect to GND	0.5 to +4.6	V
V_TERM⁽²⁾	VDDQ Terminal Voltage with Respect to GND	0.5 to VCC+0.5	V
VTERM⁽²⁾(INPUTS and I/O's)	Input and I/O Terminal Voltage with Respect to GND	65 to +150	°C
IOUT	DC Output Current	50 to +50	°C
T_STG	Continuous Clamp Current, VI < 0 or VI > VCC	-65 to +150	mA
TJ_N	Junction Temperature	+ 150	mA
IOK	Continuous Clamp Current, VO < 0	-50	mA
ICC ISS	Continuous Current through VCC or GND	±100	mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.

IDT74ALVC16841 Features

• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages

IDT74ALVC16841 Typical Application

• 3.3V high speed systems
• 3.3V and lower voltage computing systems

IDT74ALVC16841 Connection Diagram

IDT74ALVC244 General Description

This octal buffer/driver is built using advanced dual metal CMOS technology. The ALVC244 is organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

The ALVC244 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

IDT74ALVC244 Maximum Ratings

Symbol	Description	Max	Unit
V_TERM⁽²⁾	Terminal Voltage with Respect to GND	0.5 to +4.6	V
V_TERM⁽³⁾	Terminal Voltage with Respect to GND	0.5 to V_CC+0.5	V
T_STG	Storage Temperature	65 to +150	°C
I_OUT	DC Output Current	50 to +50	mA
I_IK	Continuous Clamp Current, V_I < 0 or V_I > V_CC	±50	mA
I_OK	Continuous Clamp Current, V_O < 0	50	mA
I_CC I_SS	Continuous Current through each V_CC or GND	±100	mA

IDT74ALVC244 Features

• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• V_CC = 3.3V ± 0.3V, Normal Range
• V_CC= 2.7V to 3.6V, Extended Range
• V_CC = 2.5V ± 0.2V
• CMOS power levels (0.4 W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in QSOP, SOIC, SSOP, and TSSOP packages

IDT74ALVC244 Typical Application

• 3.3V high speed systems
• 3.3V and lower voltage computing systems

IDT74ALVC244 Connection Diagram

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