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IDT74ALVCHR16270PF, IDT74ALVCHR16409PF, IDT74ALVCHR16501

Table of contents:
Info of IDT74ALVCHR16270PF
Info of IDT74ALVCHR16409PF
Info of IDT74ALVCHR16501

IDT74ALVCHR16270PF, IDT74ALVCHR16409PF, IDT74ALVCHR16501 Selling Leads, Datasheet

MFG:30 Package Cooled:IDT D/C:N/A

IDT74ALVCHR16270PF, IDT74ALVCHR16409PF, IDT74ALVCHR16501 Picture

IDT74ALVCHR16270PF, IDT74ALVCHR16409PF, IDT74ALVCHR16501 Datasheet download

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Part Number: IDT74ALVCHR16270PF

MFG: 30

Package Cooled: IDT

D/C: N/A

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IDT74ALVCHR16501 General Description

This 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/ flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state.

Data flow from B to A is similiar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and OEBA is active low).

The ALVCHR16501 has series resistors in the device output structure which will significantly reduce reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels.

The ALVCHR16501 has "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.

IDT74ALVCHR16501 Maximum Ratings

Description	Symbol	Max	unit
Terminal Voltage with Respect to GND	VTERM⁽²⁾	0.5 to +4.6	V
Terminal Voltage with Respect to GND	VTERM⁽³⁾	0.5 to V_CC+0.5	V
Storage Temperature	T_STG	65 to +150	° C
DC Output Current	I_OUT	50 to +50	mA
Continuous Clamp Current, VI < 0 or VI > V_CC	I_IK	±50	mA
Continuous Clamp Current, V_O< 0	I_OK	50	mA
Continuous Current through each V_CC or G_ND	I_CC I_SS	±100	mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.

IDT74ALVCHR16501 Features

• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages

IDT74ALVCHR16501 Typical Application

• 3.3V high speed systems
• 3.3V and lower voltage computing systems

IDT74ALVCHR16501 Connection Diagram

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