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IDT74LVC163A, IDT74LVC16501A, IDT74LVC16501APA8

Table of contents:
Info of IDT74LVC163A
Info of IDT74LVC16501A
Info of IDT74LVC16501APA8

IDT74LVC163A, IDT74LVC16501A, IDT74LVC16501APA8 Selling Leads, Datasheet

MFG:IDT Package Cooled:N/A D/C:09+

IDT74LVC163A, IDT74LVC16501A, IDT74LVC16501APA8 Picture

IDT74LVC163A, IDT74LVC16501A, IDT74LVC16501APA8 Datasheet download

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Part Number: IDT74LVC163A

MFG: IDT

Package Cooled: N/A

D/C: 09+

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IDT74LVC163A General Description

The LVC163A is a synchronous presettable binary counter, which features an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all the flip-flops clocked simultaniously on the positive-going edge of the clock (CP).

Outputs (Q0 to Q3) may be preset to a high or low level. A low level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A low level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to low level after the next positivegoing transition on the clock (CP) input (provided that the set-up and hold time requirements for PE are met).

This action occurs regardless of the levels of CP, PE, CET, and CEP inputs. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate.

The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be high to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a high output pulse of a duration approximately equal to a high level output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula:

IDT74LVC163A Maximum Ratings

Symbol	Description	Max	Unit
VTERM	Terminal Voltage with Respect to GND	0.5 to +6.5	V
TSTG	Storage Temperature	65 to +150	°C
IOUT	DC Output Current	50 to +50	mA
IIK IOK	Continuous Clamp Current, VI < 0 or VO < 0	50	mA
ICC ISS	Continuous Current through each VCC or GND	±100	mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

IDT74LVC163A Features

• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4 W typ. static)
• Rail-to-Rail output swing for increased noise margin
• All inputs, outputs, and I/Os are 5V tolerant
• Supports hot insertion
• Available in QSOP, SOIC, SSOP, and TSSOP packages
• High Output Drivers: ±24mA
• Reduced system switching noise

IDT74LVC163A Typical Application

• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems

IDT74LVC163A Connection Diagram

IDT74LVC16501A General Description

The LVC16501A is built using advanced dual metal CMOS technology. This high-speed, low power 18-bit registered bus transceiver combines Dtype latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by outputenable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B port to A port is similar but requires using OEBA, LEBA and CLKBA. Flowthrough organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin.

The LVC16501A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system.

IDT74LVC16501A Maximum Ratings

Symbol	Description	Max	Unit
VTERM	Terminal Voltage with Respect to GND	0.5 to +6.5	V
TSTG	Storage Temperature	65 to +150	°C
IOUT	DC Output Current	50 to +50	mA
IIK IOK	Continuous Clamp Current, VI < 0 or VO < 0	50	mA
ICC ISS	Continuous Current through each VCC or GND	±100	mA

IDT74LVC16501A Features

• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4 W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages

IDT74LVC16501A Typical Application

·5V and 3.3V mixed voltage systems
·Data communication and telecommunication systems

IDT74LVC16501A Connection Diagram

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