MFG:IDT Package Cooled:SSOP D/C:03+
IDT74LVC16543APV, IDT74LVC16601A, IDT74LVC16601APF Datasheet download
MFG: IDT
Package Cooled: SSOP
D/C: 03+
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PDF/DataSheet Download
Datasheet: IDT 79R3081
File Size: 914564 KB
Manufacturer: IDT
Download : Click here to Download
PDF/DataSheet Download
Datasheet: IDT74LVC16601A
File Size: 71884 KB
Manufacturer: IDT
Download : Click here to Download
PDF/DataSheet Download
Datasheet: IDT 79R3081
File Size: 914564 KB
Manufacturer: IDT
Download : Click here to Download
The LVC16601A 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. This 18-bit universal bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/ flip-flop on the LOW-to-HIGH transition of CLKAB. Output enable OEAB is active low. WhenOEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA.
All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC16601A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
|
Symbol |
Description |
Max |
Unit |
|
VTERM |
Terminal Voltage with Respect to GND |
0.5 to +6.5 |
V |
|
TSTG |
Storage Temperature |
65 to +150 |
°C |
|
IOUT |
DC Output Current |
50 to +50 |
mA |
|
IIK IOK |
Continuous Clamp Current, VI < 0 or VO < 0 |
50 |
mA |
|
ICC ISS |
Continuous Current through each VCC or GND |
±100 |
mA |
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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