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IDT74LVC652APG, IDT74LVC74A, IDT74LVC74APY

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Info of IDT74LVC652APG
Info of IDT74LVC74A
Info of IDT74LVC74APY

IDT74LVC652APG, IDT74LVC74A, IDT74LVC74APY Selling Leads, Datasheet

MFG:IDT Package Cooled:TSSOP D/C:99+

IDT74LVC652APG, IDT74LVC74A, IDT74LVC74APY Picture

IDT74LVC652APG, IDT74LVC74A, IDT74LVC74APY Datasheet download

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Part Number: IDT74LVC652APG

MFG: IDT

Package Cooled: TSSOP

D/C: 99+

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IDT74LVC74A General Description

This dual positive-edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive, data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The LVC74A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment.

IDT74LVC74A Maximum Ratings

Symbol	Description	Max	Unit
VTERM	Terminal Voltage with Respect to GND	0.5 to +6.5	V
TSTG	Storage Temperature	65 to +150	°C
IOUT	DC Output Current	50 to +50	mA
IIK IOK	Continuous Clamp Current, VI < 0 or VO < 0	50	mA
ICC ISS	Continuous Current through each VCC or GND	±100	mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

IDT74LVC74A Features

• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4 W typ. static)
• Rail-to-Rail output swing for increased noise margin
• All inputs, outputs, and I/Os are 5V tolerant
• Supports hot insertion
• Available in QSOP, SOIC, SSOP, and TSSOP packages

IDT74LVC74A Typical Application

• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems

IDT74LVC74A Connection Diagram

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