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Description The IRS2153(1)D is based on the popular IR2153 selfoscillating half-bridge gate driver IC using a more advanced silicon platform, and incorporates a high voltage half-bridge gate driver with a front end oscillator similar to the industry standard CMOS 555 timer. HVIC and latch immune CMOS technologies enable rugged monolithic construction. The output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. Noise immunity is achieved with low di/dt peak of the gate drivers.
IRS2153DPBF Maximum Ratings
Symbol
Definition
Min.
Max.
Units
VB
VS
VHO
VLO
High side floating supply voltage
High side floating supply offset voltage
High side floating output voltage
Low side output voltage
-0.3
VB - 25
VS 0.3
-0.3
625
VB + 0.3
VB + 0.3
VCC + 0.3
V
IRT
RT pin current
-5
5
mA
VRT
VCT
RT pin voltage
CT pin voltage
-0.3
-0.3
VCC + 0.3
VCC + 0.3
V
ICC
IOMAX
Supply current (Note 1)
Maximum allowable current at LO and HO due to external power transistor Miller effect.
---
-500
20
500
mA
dVS/dt
Allowable offset voltage slew rate
-50
50
V/ns
PD
PD
Maximum power dissipation @ TA +25 , 8-Pin DIP
Maximum power dissipation @ TA +25 , 8-Pin SOIC
---
---
1.0
0.625
W
RthJA
RthJA
Thermal resistance, junction to ambient, 8-Pin DIP
Thermal resistance, junction to ambient, 8-Pin SOIC
---
---
85
128
/W
TJ
TS
TL
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
-55
-55
---
150
150
300
Note 1: This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.4 V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section.
IRS2153DPBF Features
· Integrated 600 V half-bridge gate driver · CT, RT programmable oscillator · 15.4 V Zener clamp on VCC · Micropower startup · Non-latched shutdown on CT pin (1/6th VCC) · Internal bootstrap FET · Excellent latch immunity on all inputs and outputs · +/- 50 V/ns dV/dt immunity · ESD protection on all pins · 8-lead SOIC or PDIP package · Internal deadtime