ISL6532BCR, ISL6532CCR-T, ISL6532CR Selling Leads, Datasheet
MFG:INTERSIL Package Cooled:QFN20 D/C:03+
ISL6532BCR, ISL6532CCR-T, ISL6532CR Datasheet download

Part Number: ISL6532BCR
MFG: INTERSIL
Package Cooled: QFN20
D/C: 03+
MFG:INTERSIL Package Cooled:QFN20 D/C:03+
ISL6532BCR, ISL6532CCR-T, ISL6532CR Datasheet download

MFG: INTERSIL
Package Cooled: QFN20
D/C: 03+
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PDF/DataSheet Download
Datasheet: ISL6532BCR
File Size: 405199 KB
Manufacturer: INTERSIL
Download : Click here to Download
PDF/DataSheet Download
Datasheet: ISL12026
File Size: 465643 KB
Manufacturer: INTERSIL
Download : Click here to Download
PDF/DataSheet Download
Datasheet: ISL6532CR
File Size: 372736 KB
Manufacturer: INTERSIL
Download : Click here to Download
The ISL6532 provides a complete ACPI compliant power solution for up to 4 DIMM dual channel DDR/DDR2 memory systems. Included are both a synchronous buck controller and integrated LDO to supply VDDQ with high current during S0/S1 states and standby current during S3 state. During Run mode, a fully integrated sink-source regulator generates an accurate (VDDQ/2) high current VTT voltage without the need for a negative supply. A buffered version of the VDDQ/2 reference is provided as VREF.
The switching PWM controller drives two N-Channel MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter uses voltagemode control with fast transient response. Both the switching regulator and integrated standby LDO provide a maximum static regulation tolerance of ±2% over line, load, and temperature ranges. The output is user-adjustable by means of external resistors down to 0.8V.
Switching the memory core output between the PWM regulator and the standby LDO during state transitions is accomplished smoothly via the internal ACPI control circuitry. The NCH signal provides synchronized switching of a backfeed blocking switch during the transitions eliminating the need to route 5V Dual to the memory supply.
An integrated soft-start feature brings VDDQ into regulation in a controlled manner when returning to S0/S1 state from S4/S5 or mechanical off states. During S0 the PGOOD signal indicates that all supplies are within spec and operational.
Each output is monitored for under and over-voltage events. Current limiting is included on the VTT and VDDQ standby regulators. Thermal shutdown is integrated.

