ISL12025

Voltage on VDD, VBAT, SCL, SDA, and RESET pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on X1 and X2 pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V
Latchup (Note 1) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85 
ESD Rating (MIL-STD-883, Method 3014) . . . . . . . . . . . . . . .>±2kV
ESD Rating (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . .>175V
Thermal Information
Thermal Resistance (Note 2)                                           _JA (  /W)
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . .  . .  . .  . .  . . . . . 120
8 Ld TSSOP Package . . . . . . . . . . . . . . . . . .  . .  . .  . .  . . . . . . . 140
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65   to +150 
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300 

*CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.
2. _JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.