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KBE00S003M-D411, KBF-460R-12A1, KBIC-951A

KBE00S003M-D411, KBF-460R-12A1, KBIC-951A Selling Leads, Datasheet

MFG:BGA  Package Cooled:06+  D/C:06+

KBE00S003M-D411, KBF-460R-12A1, KBIC-951A Picture

KBE00S003M-D411, KBF-460R-12A1, KBIC-951A Datasheet download

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Part Number: KBE00S003M-D411

 

MFG: BGA

Package Cooled: 06+

D/C: 06+

 

 

 
 
 
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  • KBE00F005A-D411

  • Vendor: SAMSUNG Pack: BGA D/C: 05+& Qty: 1700 Note: new and orignal  Adddate: 2024-03-29
  • Inquire Now
  • XYC ELECTRONIC COMPANY   China
    Contact: Ms.AiXun   MSN:sale.ic@hotmail.com
    Tel: 86-0755-61617705
    Fax: 86-0755-61617706
    (0)

About KBE00S003M-D411

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Datasheet: KBE00S003M-D411

File Size: 1851778 KB

Manufacturer: SAMSUNG [Samsung semiconductor]

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KBE00S003M-D411 General Description

The KBE00S003M is a Multi Chip Package Memory which combines 2Gbit Nand Flash Memory(organized with two pieces of 1G bit Nand Flash Memory) and 512Mbit synchronous high data rate Dynamic RAM.(organized with two pieces of 256Mbit Mobile SDRAM) 2Gbit NAND Flash memory is organized as 256M x8 bits and 512Mbit SDRAM is organized as 8M x16 bits x4 banks.

In 2Gbit NAND Flash, Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200s on the 528-bytes and an erase operation can be performed in typical 2ms on a 16Kbytes block. Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/ output as well as command input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.

This device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

In 512Mbit SDRAM, Synchronous design make a device controlled precisely with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

The KBE00S003M is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This device is available in 107-ball FBGA Type.

KBE00S003M-D411 Maximum Ratings

Parameter
Symbol
Rating
Unit
Voltage on any pin relative to VSS
VIN/OUT
-0.6 to +4.6
V
VCC/VCCQ
-0.6 to +4.6
Temperature Under Bias
TBIAS
-40 to +125
°C
Storage Temperature
TSTG
-65 to +150
°C
Short Circuit Current
IOS
5
mA


NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

KBE00S003M-D411 Features

<Common>
• Operating Temperature : -25°C ~ 85°C
• Package : 107-ball FBGA Type - 12x14mm, 0.8mm pitch
<NAND>
• Power Supply Voltage : 2.5~2.9V
• Organization
- Memory Cell Array : (256M + 8,192K)bits x 8bits
- Data Register : (512 + 16)bits x 8bits
• Automatic Program and Erase
- Page Program : (512 + 16)bits x 8bits
- Block Erase : (16K + 512)Bytes
• Page Read Operation
- Page Size : (512 + 16)Bytes
- Random Access : 15s(Max.)
- Serial Page Access : 50ns(Min.)
• Fast Write Cycle Time
- Program time : 200s(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Intelligent Copy-Back
• Unique ID for Copyright Protection
<Mobile SDRAM>
• Power Supply Voltage : 1.7~1.95V
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
-. DS (Driver Strength)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• 1/CS Support.

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