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M36L0T7050T0, M36L0T7050T1ZAQ, M36L0T7050T1ZAQF

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Info of M36L0T7050T0
Info of M36L0T7050T1ZAQ
Info of M36L0T7050T1ZAQF

M36L0T7050T0, M36L0T7050T1ZAQ, M36L0T7050T1ZAQF Selling Leads, Datasheet

MFG:STM Package Cooled:BGA D/C:04+

M36L0T7050T0, M36L0T7050T1ZAQ, M36L0T7050T1ZAQF Picture

M36L0T7050T0, M36L0T7050T1ZAQ, M36L0T7050T1ZAQF Datasheet download

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Part Number: M36L0T7050T0

MFG: STM

Package Cooled: BGA

D/C: 04+

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M36L0T7050T0 General Description

The M36L0T7050T0 and M36L0T7050B0 combine two memory devices in a Multi-Chip Package: Ma 128-Mbit, Multiple Bank Flash memory, the M30L0T7000T0 or M30L0T7000B0, and a 32-Mbit PseudoSRAM, the M69AW048B. Recommended operating conditions do not allow more than one memory to be active at the same time.

The memory is offered in a Stacked TFBGA88 (8x10mm, 8x10 ball array, 0.8mm pitch) package. In addition to the standard version, the packages are also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive.

All packages are compliant with Lead-free soldering processes.

The memory is supplied with all the bits erased (set to '1').

M36L0T7050T0 Maximum Ratings

Symbol	Parameter	Value		Unit
Symbol	Parameter	Min	Max	Unit
T_A	Ambient Operating Temperature	25	85
T_BIAS	Temperature Under Bias	25	85
T_STG	Storage Temperature	55	125
T_LEAD	Lead Temperature during Soldering		(1)
V_IO	Input or Output Voltage	0.5	3.6	V
V_DDF	Flash Memory Core Supply Voltage	0.2	2.5	V
V_DDF, V_DDP	PSRAM and Input/Output Supply Voltages	0.2	3.6	V
V_PPF	Flash Program Voltage	0.2	14	V
I_O	Output Short Circuit Current		100	mA
t_VPPFH	Time for V_PPF at V_PPFH		100	hours

Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.

M36L0T7050T0 Features

` MULTI-CHIP PACKAGE
   1 die of 128Mbit (8Mx16, Multiple Bank, Multi-level, Burst) Flash Memory
   1 die of 32Mbit (2Mx16) Pseudo SRAM
` SUPPLY VOLTAGE
   V_DDF = 1.7 to 2V
   V_DDP = V_DDQ = 2.7 to 3.3V
   VPP = 9V for fast program (12V tolerant)
` ELECTRONIC SIGNATURE
   Manufacturer Code: 20h
   Device Code (Top Flash Configuration) M36L0T7050T0: 88C4h
   Device Code (Bottom Flash Configuration) M36L0T7050B0: 88C5h
` PACKAGE
   Compliant with Lead-Free Soldering Processes
   Lead-Free Versions
FLASH MEMORY
` SYNCHRONOUS / ASYNCHRONOUS READ
   Synchronous Burst Read mode: 50MHz
   Asynchronous Page Read mode
   Random Access: 90ns
` SYNCHRONOUS BURST READ SUSPEND
` PROGRAMMING TIME
   10µs typical Word program time using Write to Buffer and Program
` MEMORY ORGANIZATION
   Multiple Bank Memory Array: 8 Mbit Banks
   Parameter Blocks (Top or Bottom location)
` DUAL OPERATIONS
   program/erase in one Bank while read in others
   No delay between read and write operations
` SECURITY
   64 bit unique device number
   2112 bit user programmable OTP Cells
` BLOCK LOCKING
   All blocks locked at power-up
   Any combination of blocks can be locked with zero latency
   WP for Block Lock-Down
   Absolute Write Protection with V_PP = V_SS
` COMMON FLASH INTERFACE (CFI)
` 100,000 PROGRAM/ERASE CYCLES per BLOCK
PSRAM
` ACCESS TIME: 70ns
` LOW STANDBY CURRENT: 100µA
` DEEP POWER-DOWN CURRENT: 10µA
` BYTE CONTROL: UB_P/LB_P
` PROGRAMMABLE PARTIAL ARRAY
` 8 WORD PAGE ACCESS CAPABILITY: 18ns
` POWER-DOWN MODES
   Deep Power-Down
   4 Mbit Partial Array Refresh
   8 Mbit Partial Array Refresh
   16 Mbit Partial Array Refresh

M36L0T7050T0 Connection Diagram

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