M66220FP, M66220SP, M66222FP Selling Leads, Datasheet
MFG:MITSUBISHI Package Cooled:2007+ D/C:1200
M66220FP, M66220SP, M66222FP Datasheet download
Part Number: M66220FP
MFG: MITSUBISHI
Package Cooled: 2007+
D/C: 1200
M66220FP, M66220SP, M66222FP
- Table of contents:
Info of M66220FP
Info of M66220SP
Info of M66222FP
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About M66220FP
PDF/DataSheet Download
Datasheet: M66220FP
File Size: 141500 KB
Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
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About M66220SP
PDF/DataSheet Download
Datasheet: M66220SP
File Size: 141500 KB
Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
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About M66222FP
PDF/DataSheet Download
Datasheet: M66222FP
File Size: 110468 KB
Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
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M66220FP General Description
The M66220 is a mail box that incorporates a complete CMOS shared memory cell of 256 ´ 8-bit configuration using high-performance silicon gate CMOS process technology, and is equipped with two access
ports of A and B.
Access ports A and B are equipped with independent addresses CS,WE and OE control pins and I/O pins to allow independent and asynchronous read/write operations from/to shared memory individually. This product also incorporates a port adjustment arbitration function in address contention from both ports.
M66220FP Maximum Ratings
|
Symbol |
Parameter |
Conditions |
Ratings |
Unit |
| Vcc | Supply voltage |
When defining GND pin as a reference. |
-0.3to +7.0 |
V |
| VI | Input voltage |
-0.3toVcc+0.3 |
V | |
| Vo | Output voltage |
0toVcc |
V | |
| Pd | Maximum power dissipation | Ta = 25 °C |
700 |
mW |
| Tstg | Storage temperature |
-65 to +150 |
°C |
M66220FP Features
• Memory configuration of 256 ´ 8 bits
• High-speed access, address access time 40ns (typ.)
• Complete asynchronous accessibility from ports A and B
• Completely static operation
• Built-in port arbitration function
• Low power dissipation CMOS design
• 5V single power supply
• Not Readyoutput pin is provided (open drain output)
• TTL direct-coupled I/O
• 3-state output for I/O pins
• High-speed access, address access time 40ns (typ.)
• Complete asynchronous accessibility from ports A and B
• Completely static operation
• Built-in port arbitration function
• Low power dissipation CMOS design
• 5V single power supply
• Not Readyoutput pin is provided (open drain output)
• TTL direct-coupled I/O
• 3-state output for I/O pins
M66220FP Typical Application
Inter-MPU data transfer memory, buffer memory for image processing system.
M66220FP Connection Diagram
M66220SP General Description
The M66220 is a mail box that incorporates a complete CMOS shared memory cell of 256 ´ 8-bit configuration using high-performance silicon gate CMOS process technology, and is equipped with two access
ports of A and B.
Access ports A and B are equipped with independent addresses CS,WE and OE control pins and I/O pins to allow independent and asynchronous read/write operations from/to shared memory individually. This product also incorporates a port adjustment arbitration function in address contention from both ports.
M66220SP Maximum Ratings
|
Symbol |
Parameter |
Conditions |
Ratings |
Unit |
| Vcc | Supply voltage |
When defining GND pin as a reference. |
-0.3to +7.0 |
V |
| VI | Input voltage |
-0.3toVcc+0.3 |
V | |
| Vo | Output voltage |
0toVcc |
V | |
| Pd | Maximum power dissipation | Ta = 25 °C |
700 |
mW |
| Tstg | Storage temperature |
-65 to +150 |
°C |
M66220SP Features
• Memory configuration of 256 ´ 8 bits
• High-speed access, address access time 40ns (typ.)
• Complete asynchronous accessibility from ports A and B
• Completely static operation
• Built-in port arbitration function
• Low power dissipation CMOS design
• 5V single power supply
• Not Readyoutput pin is provided (open drain output)
• TTL direct-coupled I/O
• 3-state output for I/O pins
• High-speed access, address access time 40ns (typ.)
• Complete asynchronous accessibility from ports A and B
• Completely static operation
• Built-in port arbitration function
• Low power dissipation CMOS design
• 5V single power supply
• Not Readyoutput pin is provided (open drain output)
• TTL direct-coupled I/O
• 3-state output for I/O pins
M66220SP Typical Application
Inter-MPU data transfer memory, buffer memory for image processing system.
M66220SP Connection Diagram
M66222FP General Description
The M66222 is a mail box that incorporates two complete CMOS shared memory cells of 128×8-bit configuration using highperformance silicon gate CMOS process technology, and are equipped with two access ports of A and B.
Access ports A and B are equipped with independent addresses CS , WE and OE control pins and I/O pins to allow independent and asynchronous read/write operations individually. This product exclusively performs a write operation from A port and a read operation from B port for one memory, and a read operation from A port and a write operation from B port for the other memory.
M66222FP Maximum Ratings
|
Symbol |
Parameter |
Conditions |
Rating |
Unit |
| Vcc | Supply voltage |
When defining GND pin as a reference. |
-0.3to+7.0 |
V |
| VI | Input voltage |
0.3 toVcc+0.3 |
V | |
| Vo | Output voltage |
0 toVcc |
V | |
| Pd | Maximum power dissipation | Ta=25 °C |
700 |
mW |
| Tstg | Storage temperature |
-65 to +150 |
°C |
M66222FP Features
• Memory configuration of 128 × 8 bits × 2 memory areas
• High-speed access, address access time 40ns (typ.)
• Complete asynchronous accessibility from ports A and B
• Fixed read/write access ports for memory
• Completely static operation
• Low power dissipation CMOS design
• 5V single power supply
• TTL direct-coupled I/O
• 3-state output for I/O pins
• High-speed access, address access time 40ns (typ.)
• Complete asynchronous accessibility from ports A and B
• Fixed read/write access ports for memory
• Completely static operation
• Low power dissipation CMOS design
• 5V single power supply
• TTL direct-coupled I/O
• 3-state output for I/O pins
M66222FP Typical Application
Inter-MCU data transfer memory, communication buffer memory
M66222FP Connection Diagram
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