M66307SP, M66310, M66310FP Selling Leads, Datasheet
MFG:MIT Package Cooled:DIP 32 D/C:7527
M66307SP, M66310, M66310FP Datasheet download
Part Number: M66307SP
MFG: MIT
Package Cooled: DIP 32
D/C: 7527
MFG:MIT Package Cooled:DIP 32 D/C:7527
M66307SP, M66310, M66310FP Datasheet download
MFG: MIT
Package Cooled: DIP 32
D/C: 7527
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PDF/DataSheet Download
Datasheet: M66307SP
File Size: 239090 KB
Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: M66310FP
File Size: 226553 KB
Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: M66310FP
File Size: 226553 KB
Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
Download : Click here to Download
The M66307SP/FP is an integrated circuit consisting of a line buffer with static memory, manufactured by the silicon gate CMOS process,which satisfies A3-paper 400DPI requirements. It converts the stored data from the 16-bit MPU bus into serial data and outputs it at a transfer rate of up to 10Mbps synchronously with the external data request clock or an arbitrary continuous clock.
Symbol |
Parameter |
Condition |
Rating |
Unit |
Vcc | Supply voltage |
0.3to+7.0 |
V | |
VI | Input voltage |
-0.3toVcc+0.3 |
V | |
Vo | Output voltage |
0toVcc |
V | |
Pd | Power dissipation | Ta=25°C |
700 |
mW |
Tstg | Storage temperature |
-65to+150 |
°C |
• 16-bit MPU bus compatible
• Writing data via DMAC is possible
• 320-word (5,120-bit) static RAM
• Data output rate of up to 10Mbps
• Built-in function to add fixed data of a specified length at the beginning of output data (Fixed data: Continuous High bit or Low bit data)
• The output format can be selected between FIFO or LIFO.
• The output method can be selected from two:
(1) Synchronized with an arbitrary continuous clock (IN) on the system side; the frequency of clock output (CLK/OUT) can be divided by 1, 2, 4, 8, or 16.
(2) Synchronized with the data request clock (CLK IN) on the peripheral equipment side.
• Up to two devices can be cascaded.
(1) Toggle configuration
(2) 32-bit bus configuration
• High fan-out outputs (CLK/OUT, DATA OUT).
Io=±24mA
(±4mA for INTR and DREQ
±8mA for BUSY/ORDY)