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ML670100-001TC, ML671000, ML672

Table of contents:
Info of ML670100-001TC
Info of ML671000
Info of ML672

ML670100-001TC, ML671000, ML672 Selling Leads, Datasheet

MFG:OKI Package Cooled:QFP D/C:02+

ML670100-001TC, ML671000, ML672 Datasheet download

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Part Number: ML670100-001TC

MFG: OKI

Package Cooled: QFP

D/C: 02+

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ML671000 General Description

The ML671000 is a high-performance CMOS 32-bit microcontroller combining a RISC based, 32-bit CPU core - the ARM7TDMITM - with USB device controller, memory and peripherals.

The built-in USB device controller which is based on USB1.1 Full-speed (12 Mbps) makes interface with PCs or other devices by USB. The ML671000, which provides the 32-bit data processing capability and built-in peripheral functions performed by UART, serial ports, 16-bit timers, a DMA controller, and a memory controller,is a single-chip microcontroller idealy suited to PC peripheral equipment and communication terminal control applications.

ML671000 Maximum Ratings

Parameter	Symbol	Condition	Rated value	Unit
Supply voltage	V_DD	V_DD GND = 0 V T_a = 25°C	−0.3 to +4.6	V
Input voltage	V_IN		−0.3 to V_DD +0.3	V
Output current	I_O		12	mA
Power dissipation	P_D		1	W
Storage temperature	T_STG	-	55 to +150	°C

ML671000 Features

CPU	RISC 32-bit CPU (ARM7TDMI) Executable 32-bit instructions and 16-bit instructions General registers: 32-bit × 31 registers Built-in multiplier Little-endian format
Memory Spaces	Internal RAM : 4K bytes External ROM, RAM, I/O : 26M bytes External DRAM : 32M bytes
I/O Ports	I/O pins: 64 pins (I/O directions are specified at the bit level)
Timers	16-bit flexible timer × 2ch (auto-reload, compare-output, PWM, capture modes) 16-bit auto-reload timer × 2ch 12-bit watchdog timer
Serial Ports	UART (16550A equivalent) × 1ch, UART/synchronous serial × 1ch
USB Device Controller	USB1.1 compliant, support full-speed (12 Mbps) Transmission type: control, bulk, isochronous, interrupt Remote wakeup function Adaptable to USB bus powered devices Four endpoint addresses Endpoint FIFO size EP0 64 bytes × 2 (transmit/receive) EP1 64 bytes × 1 (transmit-receive) EP2 64 bytes × 2 (transmit-receive, 2 levels) EP3 256 bytes × 2 (transmit-receive, 2 levels)
DMA Controller	× 2ch Single and Dual addressing modes Cycle steal and Burst transfers 8- or 16-bit data transfers Maximum transferring: 65536 times Addressing area: 64M bytes

Interrupt Controller	Interrupt sources: 22 (13 internal , 9 external ) Interrupt priority: 8 levels
Memory Controller	Direct connection to ROM, SRAM, DRAM and I/O. 4-bank memory control ROM, RAM, I/O × 2 banks; DRAM × 2 banks Access wait control parameters for each bank.
Other	Arbitration of external bus request Power saving functions Standby modes: HALT and STOP modes Clock gears: Selection of 1/2 OSC, 1/1 OSC, OSC ×2 Onboard debugging is possible with JTAG interface. Built-in PLL: × 4
Power Supply Voltage	3.0 to 3.6 V
Operating Frequency	CPU: 6, 12, 24 MHz; USB: 48 MHz @12 MHz (Operating USBC) CPU: 4 to 24 MHz (Non-Operating USBC)
Operating Temperature Range	−10°C to +70°C
Package	128-pin plastic QFP (QFP128-P-1420-0.50-K)

ML671000 Connection Diagram

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