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MPC9992, MPC9992FAR2, MPC9993

Table of contents:
Info of MPC9992
Info of MPC9992FAR2
Info of MPC9993

MPC9992, MPC9992FAR2, MPC9993 Selling Leads, Datasheet

MFG:MOTO Package Cooled:08+ D/C:1000

MPC9992, MPC9992FAR2, MPC9993 Datasheet download

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Part Number: MPC9992

MFG: MOTO

Package Cooled: 08+

D/C: 1000

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MPC9992 General Description

The MPC9992 utilizes PLL technology to frequency lock its outputs onto an input reference clock. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9992 features frequency programmability between the three output banks outputs as well as the output to input relationships. Output frequency ratios of 2:1, 3:1, 3:2 and 5:2 can be realized. The two banks of outputs and the feedback frequency divider can be programmed by the FSEL[2:0] pins of the device. The VCO_SEL pin provides an extended PLL input reference frequency range.

The SYNC pulse generator monitors the phase relationship between the QA[3:0] and QB[2:0] output banks. The SYNC generator output signals the coincident edges of the two output banks. This feature is useful for non binary relationships between output frequencies.

The REF_SEL pin selects the differential PECL compatible input pair or crystal oscillator interface as the reference clock signal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.

The MPC9992 requires an external reset signal for start-up and for PLL recovery in case the reference input is interrupted. Assertion of the reset signal forces all outputs to the logic low state.

The MPC9992 is fully 3.3V compatible and requires no external loop filter components. The differential clock input (PCLK) is PECL compatible and all control inputs accept LVCMOS compatible signals while the outputs provide PECL compatible levels with the capability to drive terminated 50 transmission lines.

The device is pin and function compatible to the MPC992 and is packaged in a 32-lead LQFP package. 1. Final specification of this parameter is pending characterization.

MPC9992 Maximum Ratings

Symbol	Characteristics	Min	Max	Unit	Condition
V_CC	Supply Voltage	-0.3	3.6	V
V_IN	DC Input Voltage	-0.3	V_CC+0.3	V
V_OUT	DC Output Voltage	-0.3	V_CC+0.3	V
I_IN	DC Input Current		±20	mA
I_OUT	DC Output Current		±50	mA
T_S	Storage Temperature	-65	125

MPC9992 Features

• 7 differential outputs, PLL based clock generator
• SiGe technology supports minimum output skew (max. 150 ps¹)
• Supports up to two generated output clock frequencies with a maximum clock frequency up to 400 MHz
• Selectable crystal oscillator interface and PECL compatible clock input
• SYNC pulse generation
• PECL compatible differential clock inputs and outputs
• Single 3.3V (PECL) supply
• Ambient temperature range 0 to +70
• Standard 32 lead LQFP package
• Pin and function compatible to the MPC992

MPC9992 Typical Application

The MPC9992 has a system synchronization pulse output QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC9992 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logichigh) one QA period in duration after the coincident rising edges of the QA and QB outputs. The placement of the pulse is dependent on the QA and QB output frequencies ratio. Table 2 shows the waveforms for the QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank B outputs.

MPC9992 Connection Diagram

MPC9993 General Description

The MPC9993 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section).

MPC9993 Maximum Ratings

Symbol	Characteristics	Min	Max	Unit	Condition
V_CC	Supply Voltage	0.3	3.6	V
V_IN	DC Input Voltage	0.3	V_CC+0.3	V
V_OUT	DC Output Voltage	0.3	V_CC+0.3	V
I_IN	DC Input Current		±20	mA
I_OUT	DC Output Current		±50	mA
T_S	Storage Temperature	-65	150

a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.

MPC9993 Features

• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
• 3.3V Operation
• 32Lead LQFP Packaging
• SiGe technology supports near-zero output skew

MPC9993 Connection Diagram

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