MT9041CP, MT9042, MT9042AP Selling Leads, Datasheet
MFG:MT Package Cooled:DIP D/C:04+
MT9041CP, MT9042, MT9042AP Datasheet download

Part Number: MT9041CP
MFG: MT
Package Cooled: DIP
D/C: 04+
MFG:MT Package Cooled:DIP D/C:04+
MT9041CP, MT9042, MT9042AP Datasheet download

MFG: MT
Package Cooled: DIP
D/C: 04+
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PDF/DataSheet Download
Datasheet: MT900A-UR
File Size: 211574 KB
Manufacturer: MARKTECH [Marktech Corporate]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: MT9042
File Size: 125244 KB
Manufacturer: MITEL [Mitel Networks Corporation]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: MT9042AP
File Size: 125244 KB
Manufacturer: MITEL [Mitel Networks Corporation]
Download : Click here to Download
The MT9042 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.544 MHz, or 8 kHz reference. The T1 and E1 outputs are fully compliant with AT & T TR62411 (ACCUNET® T1.5) and ETSI ETS 300 011 intrinsic jitter and jitter transfer specifications, respectively, when synchronized to primary reference input clock rates of either 1.544 MHz or 2.048 MHz.
The PLL also provides additional high speed output clocks at rates of 3.088 MHz, 4.096 MHz, 8.192 MHz, and 16.384 MHz for backplane synchronization.
| Parameter | Symbol | Min | Max | Units | |
| 1 | Supply Voltage | VDD | - 0.3 | 7 | V |
| 2 | Voltage on any pin | VI | VSS-0.3 | VDD + 0.3 | V |
| 3 | Input/Output Diode Current | IIK/OK | ±150 | mA | |
| 4 | Output Source or Sink Current | IO | ±150 | mA | |
| 5 | DC Supply or Ground Current | IDD/ISS | ±300 | mA | |
| 6 | Storage Temperature | TST | -55 | 125 | |
| 7 | Package Power Dissipation PLCC | PD | 900 | mW |
• Provides T1 and E1 clocks, and ST-BUS/GCI framing signals locked to an input reference of either 8 kHz (frame pulse), 1.544 MHz (T1), or 2.048 MHz (E1)
• Meets AT & T TR62411 and ETSI ETS 300 011 specifications for a 1.544 MHz (T1), or 2.048 MHz (E1) input reference
• Provides Time Interval Error (TIE) correction to suppress input reference rearrangement transients
• Typical unfiltered intrinsic output jitter is 0.013 UI peak-to-peak
• Jitter attenuation of 15 dB @ 10 Hz, 34 dB @ 100 Hz and 50 dB @ 5 to 40 kHz
• Low power CMOS technology

